參數(shù)資料
型號(hào)： MCM69R736AZP8R
廠商： MOTOROLA INC
元件分類： SRAM
英文描述： 4M Late Write HSTL
中文描述： 128K X 36 LATE-WRITE SRAM, 4 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 224K
代理商： MCM69R736AZP8R
MCM69R736A
MCM69R818A
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Typical
–5
Typical
–6
Typical
–7
Typical
–8
Max
Unit
Notes
Input Reference DC Voltage
Vref (dc)
VDD
VDDQ
IDD1
0.6
—
—
—
—
1.1
V
11
Core Power Supply Voltage
3.15
—
—
—
—
3.6
V
Output Driver Supply Voltage
1.4
—
—
—
—
1.6
V
Active Power Supply Current
(x18)
(x36)
—
—
350
460
330
430
300
390
290
370
450
560
mA
5
Quiescent Active Power Supply Current
IDD2
ISB1
ISB2
ISB3
—
190
190
190
190
250
mA
6, 10
Active Standby Power Supply Current
—
160
160
160
160
250
mA
7
Quiescent Standby Power Supply Current
—
140
140
140
140
230
mA
8, 10
Sleep Mode Power Supply Current
—
TBD
TBD
TBD
TBD
TBD
mA
9, 10
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.
6. VDD = VDD (max), tKHKH = dc, SS registered active.
7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.
8. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.
9. VDD = VDD (Max), tKHKH = dc, SS registered inactive, ZZ high.
10. 200 mV
≥
Vin
≥
VDDQ – 200 mV.
11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg(1)
Vin (dc)
VDIF (dc)
VCM (dc)
VX
Vref + 0.1
– 0.3
VDD + 0.3
Vref – 0.1
±
5
V
DC Input Logic Low
V
1
Input Leakage Current
—
μ
A
2
Clock Input Signal Voltage
– 0.3
VDD + 0.3
VDD + 0.6
1.1
V
Clock Input Differential Voltage
0.2
V
3
Clock Input Common Mode Voltage Range (See Figure 2)
0.68
V
4
Clock Input Crossing Point Voltage Range (See Figure 2)
0.68
1.1
V
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns). See Figure 2.
2. 0 V
≤
Vin
≤
VDDQ for all pins.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
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