參數(shù)資料
型號(hào)： MCM69R738AZP6R
廠商： MOTOROLA INC
元件分類： DRAM
英文描述： 4M Late Write 2.5 V I/O
中文描述： 128K X 36 LATE-WRITE SRAM, 3 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 213K
代理商： MCM69R738AZP6R
MCM69R738A
MCM69R820A
7
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
Output Timing Reference Level
0 to 2.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
1 V/ns (20% to 80%)
. . . . . . . . . . . . . .
1.25 V
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Timing Reference Level
Clock Input Pulse Level
R
θ
JA Device
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
1.8 V to 2.1 V
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
TBD
READ/WRITE CYCLE TIMING
(See Note 1)
MCM69R738A–5
MCM69R820A–5
MCM69R738A–6
MCM69R820A–6
MCM69R738A–7
MCM69R820A–7
MCM69R738A–8
MCM69R820A–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
s
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQX1
tKHQV
tKHQX
tKHQZ
tGLQX
5
—
6
—
7
—
8
—
ns
Clock High Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock Low Pulse Width
2
—
2.4
—
2.8
—
3.2
—
ns
Clock High to Output Low–Z
1
—
1
—
1
—
1
—
ns
2, 3
Clock High to Output Valid
—
2.5
—
3
—
3.5
—
4
ns
Clock High to Output Hold
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock High to Output High–Z
—
2.5
—
3
0
3.5
0
4
ns
2, 3
Output Enable Low to Output
Low–Z
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to Output
Valid
tGLQV
—
2.5
—
3
—
3.5
—
4
ns
Output Enable to Output Hold
tGHQX
tGHQZ
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output
High–Z
—
2.5
—
3
—
3.5
—
4
ns
2, 3
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
1
—
1
—
1
—
1
—
ns
NOTES:
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
2. This parameter is sampled and not 100% tested.
3. Measured at
±
200 mV from steady state.
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time
(even though most devices do not require it). On the oth-
er hand, responses from the memory are specified from
the device point of view. Thus, the access time is shown
as a maximum since the device never provides data lat-
er than that time.
TIMING LIMITS
DEVICE
UNDER
TEST
50
50
VDDQ/2
Figure 1. AC Test Load
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