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參數(shù)資料
| 型號： | MCM69R818AZP8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 4M Late Write HSTL |
| 中文描述： | 256K X 18 LATE-WRITE SRAM, 4 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MCM69R818AZP8 |
MCM69R736A
MCM69R818A
12
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
the output register and available at the outputs at tKHQV. Dur-
ing this same cycle a new read address can be applied to the
address pins.
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers after the next rising edge of the CK clock.
SW low deselects the output drivers immediately (on the
same cycle). Output drive is also controlled directly by output
enable, G. No clock edges are required to generate output
disable with G. G asynchronously enables the output drivers.
Output data will be valid the latter of tGLQV and tKHQV.
Outputs will begin driving at tKHQX1. Outputs will hold pre-
vious data until tKHQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable in-
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250
resistor will give an output
impedance of 50
.
Impedance updates occur continuously and the frequency
of the update is based on the subdivided K clock. Note that if
the K clock stops so does the impedance update.
The actual change in the impedance occurs in small incre-
ments and is monotonic. There are no significant distur-
bances that occur on the output because of this smooth
update method.
The impedance update is not related to any particular type
of cycle because the impedance is updated continuously and
is based on the K clock. Updates occur regardless of wheth-
er the the device is performing a read, write or a deselect
cycle and does not depend on the state of G.
At power up, the output impedance defaults to approxi-
mately 50 ohms. It will take 4,000 to 16,000 cycles for the im-
pedance to be completely updated if the programmed
impedance is much higher or lower than 50
.
The output buffers can also be programmed in a minimum
impedance configuration by connecting ZQ to VDD.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is rec-
ommended: VSS, VDD, then VDDQ. Please note, per the Ab-
solute Maximum Ratings table, VDDQ is not to exceed VDD +
0.5 V, whatever the instantaneous value of VDD. Once sup-
plies have reached specification levels, a minimum dwell of
1.0 ms with C/K clock inputs cycling is required before begin-
ning normal operations. At power up the output impedance
will be set at approximately 50
as stated above.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R818AZP8R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write HSTL |
| MCM69R818C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write HSTL |
| MCM69R818CZP4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write HSTL |
| MCM69R818CZP4.4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write HSTL |
| MCM69R818CZP4.4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write HSTL |
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