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參數(shù)資料
| 型號： | MCM69R819A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MCM69R819A |
MCM69R736C
MCM69R818C
7
MOTOROLA FAST SRAM
DC OUTPUT BUFFER CHARACTERISTICS — PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(VDD = 3.3 V, VDDQ = 1.5 V, TA = 70
°
C, See Notes 1 and 2)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
IOL
(VDDQ/2) /
[(RQ/5) + 30%]
(VDDQ/2) /
[(RQ/5) – 15%]
A
3
Output Logic High
IOH
(VDDQ/2) /
[(RQ/5) + 30%]
(VDDQ/2) /
[(RQ/5) – 15%]
A
4
Light Load Output Logic Low
VOL1
VSS
0.2
V
5
Light Load Output Logic High
VOH1
VDDQ – 0.2
VDDQ
V
6
NOTES:
1. The impedance controlled mode is expected to be used in point–to–point applications, driving high–impedance inputs.
2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
3. VOL = VDDQ/2.
4. VOH = VDDQ/2.
5. IOL
≤
100
μ
A.
6. | IOH |
≤
100
μ
A.
DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(VDD = 3.3 V +10%, –5%,
0
°
C
≤
TA
≤
70
°
C, ZQ = VDD)
(See Notes 1 and 2)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL2
VSS
0.4
V
3
Output Logic High
VOH2
VDDQ – 0.4
VDDQ
V
4
Light Load Output Logic Low
VOL3
VSS
0.2
V
5
Light Load Output Logic High
VOH3
VDDQ – 0.2
VDDQ
V
6
NOTES:
1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class I.
2. The ZQ pin is connected to VDD to enable the minimum impedance mode.
3. IOL
≥
– 8 mA
.
4. IOH
≥
8 mA.
5. IOL
≥
100
μ
A.
6.
IOH
≥
100
μ
A.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, VDD = 3.3 V +10%, –5%,
0
°
C
≤
TA
≤
70
°
C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
Cin
CI/O
CCK
4
5
pF
Input/Output Capacitance
7
8
pF
CK, CK Capacitance
4
5
pF
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