參數(shù)資料
型號(hào)： MCM69R819AZP5R
廠商： MOTOROLA INC
元件分類： DRAM
英文描述： 4M Late Write LVTTL
中文描述： 256K X 18 LATE-WRITE SRAM, 2.5 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 212K
代理商： MCM69R819AZP5R
MCM69R737A
MCM69R819A
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Typical
–5
Typical
–6
Typical
–7
Typical
–8
Max
Unit
Notes
Core Power Supply Voltage
VDD
VDDQ
IDD1
3.15
—
—
—
—
3.6
V
Output Driver Supply Voltage
3.15
—
—
—
—
3.6
V
Active Power Supply Current
(x18)
(x36)
—
—
380
450
360
420
330
390
320
370
480
550
mA
5
Quiescent Active Power Supply Current
IDD2
—
—
180
180
180
180
250
mA
6, 10
Active Standby Power Supply Current)
ISB1
—
—
170
170
170
170
250
mA
7
Quiescent Standby Power Supply Current
ISB2
—
—
150
150
150
150
230
mA
8, 10
Sleep Mode Power Supply Current
ISB3
—
30
30
30
30
50
mA
9, 10
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.
6. VDD = VDD (max), tKHKH = dc, SS registered active.
7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.
8. VDD = VDD (max), tKHKH = dc, SS registered inactive. ZZ low.
9. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ high.
10. 200 mV
≥
Vin
≥
VDDQ – 200 mV.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg(1)
Iclkg(1)
Vin
VDIF (dc)
VCM (dc)
2.0
VDD + 0.3
0.8
V
DC Input Logic Low
– 0.3
V
1
Input Leakage Current
—
±
5
μ
A
2
Clock Input Leakage Current
—
±
8
μ
A
2
Clock Input Signal Voltage
– 0.3
VDD + 0.3
VDD + 0.6
2.1
V
Clock Input Differential Voltage
0.2
V
3
Clock Input Common Mode Voltage Range (See Figure 3)
1
V
4
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. 0 V
≤
Vin
≤
VDDQ for all pins.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
DC OUTPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
Output Leakage Current
Ilkg(0)
–1.0
1.0
μ
A
Output Low Voltage
VOL
—
0.4
V
1
Output High Voltage
VOH
2.4
—
V
2
NOTES:
1. IOL = 8.0 mA.
2. IOH = – 8.0 mA.
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