參數(shù)資料
型號(hào)： MCM69R819AZP8R
廠商： MOTOROLA INC
元件分類： DRAM
英文描述： 4M Late Write LVTTL
中文描述： 256K X 18 LATE-WRITE SRAM, 3.5 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁(yè)數(shù)： 17/20頁(yè)
文件大?。?/td> 212K
代理商： MCM69R819AZP8R
MCM69R737A
MCM69R819A
17
MOTOROLA FAST SRAM
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM outputs to High–Z state. *NOT 1149.1 COMPLIANT*
IDCODE
001**
Preloads ID register and places it between TDI and TDO.
Does not affect RAM operation.
SAMPLE / PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement 1149.1 Preload function. * NOT 1149.1 COMPLIANT *
BYPASS
111
Places bypass register between TDI and TDO.
Does not affect RAM operation.
SAMPLE–Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM output drivers to High–Z.
*Instruction codes expressed in binary, MSB on left, LSB on right.
**Default instruction automatically loaded at power–up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
*Instruction codes expressed in binary, MSB on left, LSB on right.
CAPTURE–DR
EXIT1–DR
EXIT2–DR
UPDATE–DR
CAPTURE–IR
EXIT1–IR
EXIT2–IR
UPDATE–IR
SHIFT–IR
PAUSE–IR
SHIFT–DR
PAUSE–DR
TEST–LOGIC
RESET
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
0
Figure 5. TAP Controller State Diagram
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