2005-2012 Microchip Technology Inc.
DS22018F-page 23
MCP2021/2/1P/2P
Bus Interface
High Level Input Voltage
VIH(LBUS)0.6 VBB
—
18
V
Recessive state
Low Level Input Voltage
VIL(LBUS)-8
—
0.4 VBB
V
Dominant state
Input Hysteresis
VHYS
——
0.175 VBB
VVIH(LBUS) - VIL(LBUS)
Low Level Output Current
IOL(LBUS)40
—
200
mA
Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input
IPU(LBUS)5
—
180
A
~30 k
Ω internal pull-up
@ VIH (LBUS) = 0.7 VBB
Short Circuit Current
Limit
ISC
50
—
200
mA
(Note 1)
High Level Output
Voltage
VOH(LBUS)0.8 VBB
—
VBB
VVOH(LBUS) must be at least
0.8 VBB
Low Level Output Voltage
VOLLO
(LBUS)
—
0.2 VBB
V
Input Leakage Current (at
the receiver during
dominant bus level)
IBUS_PAS_DOM
-1
—
mA
Driver off,
VBUS = 0V,
VBAT = 12V
Leakage Current
(disconnected from
ground)
IBUS_NO_GND
-1
—
+1
mA
GNDDEVICE = VBAT,
0V < VBUS < 18V,
VBAT = 12V
Leakage Current
(disconnected from VBAT)
IBUS
—
10
A
VBAT = GND,
0 < VBUS < 18V,
TA = -40
°C to +85°C
50
A
TA = +85
°C to +125°C
Receiver Center Voltage
VBUS_CNT
0.475 VBB
0.5
VBB
0.525 VBB
VVBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Slave Termination
Rslave
20
30
47
k
Ω
2.2
DC Specifications (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 F
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Note 1:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0
Ω, TX = 0.4 VREG, VLBUS = VBB).
2:
For design guidance only, not tested.
3:
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.