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| 型號： | MCP2022AT-330E/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX LIN 3.3V LDO 14-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Microchip MCP20xx LIN Transceiver Overview |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 系列： | * |
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2012 Microchip Technology Inc.
DS22298A-page 5
MCP2021A/2A
1.2
Pin Descriptions
Please refer to Table 1-2 for the pinout overview.
1.2.1
VBB
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to FIGURE 1-9: “Typical
1.2.2
VREG
Positive Supply Voltage Regulator Output pin. An on-
chip LDO gives +5.0 or +3.3V 70 mA regulated voltage
on this pin.
1.2.3
VSS
Ground pin.
1.2.4
TXD
Transmit data input pin (TTL level, HV compliant,
adaptive pull-up). The transmitter reads the data
stream on TXD pin and sends it to LIN bus. The LBUS
pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
The Transmit Data Input pin has an internal adaptive
pull-up to an internally-generated 4.2V (approxi-
mately). When TXD is ‘0’, a weak pull-up (~900 k) is
used to reduce current. When TXD is ‘1’, a stronger
pull-up (~300 k) is used to maintain the logic level. A
series reverse-blocking diode allows applying TXD
input voltages greater than the internally generated
4.2V and renders TXD pin HV compliant up to 30V (see
block diagram).
1.2.5
RXD
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
1.2.6
LBUS
LIN Bus pin. LBUS is a bidirectional LIN bus Interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
ElectroMagnetic Emission, the slopes during signal
changes are controlled, and the LBUS pin has corner-
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and generates the output signal RXD that
follows the state of the LBUS. A 1st degree 160 kHz,
low-pass input filter optimizes ElectroMagnetic immu-
nity.
1.2.7
CS/LWAKE
Chip Select and Local Wake-up Input pin (TTL level,
high voltage tolerant). This pin controls the device state
transition. Refer to FIGURE 1-1: “State Diagram”.
If CS/LWAKE = 1, the device can work in OPERATION
mode (FAULT/TXE = 1) or TRANSMITTER OFF mode
(FAULT/TXE = 0).
If CS/LWAKE = 0, the device can work in POWER-
DOWN mode or READY mode.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-on Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 k) is used
to reduce current. When CS/LWAKE is ‘0’ a stronger
pull-down (~300 k) is used to maintain the logic level.
This pin may also be used as a local wake-up input
The microcontroller will set the I/O pin to control the
CS/LWAKE. An external switch, or other source, can
then
wake-up
both
the
transceiver
and
the
microcontroller.
1.2.8
FAULT/TXE
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV tolerant open drain (up to 30V).
The input section is identical with the TXD section (TTL
level, HV compliant, adaptive pull-up). Internal
adaptive pull-up maintains this input high '1' if the pin is
floating. Its state is defined as shown in TABLE 1-3:
“FAULT/TXE Truth Table”. The device is placed in
TRANSMITTER OFF mode whenever this pin is LOW
(‘0’), either from an internal fault condition or by
external drive.
If CS/LWAKE is HIGH (‘1’), the FAULT/TXE signals a
mismatch between the TXD input and the LBUS level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains LOW (‘0’)
(refer Table 1-3).
The FAULT/TXE pin sampled at a rate faster than every
10 s.
1.2.9
RESET (MCP2022A ONLY)
RESET OUTPUT pin. This pin is open drain with
~90 k pull-up to VREG. It indicates the internal volt-
age has reached a valid, stable level. As long as the
internal voltage is valid (above 0.8 VREG), this pin will
remain HIGH (‘1’); otherwise the RESET pin switches
to LOW (‘0’).
Note:
CS/LWAKE should NOT be tied directly to
the VREG pin as this could force the
MCP2021A/2A into Operation Mode
before the microcontroller is initialized.
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| MCP2022AT-500E/SL | 功能描述:LIN 收發(fā)器 LIN Transceiver + 5.0V LDO RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| MCP2022AT-500E/ST | 功能描述:LIN 收發(fā)器 LIN Transceiver + 5.0V LDO RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| MCP2022P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:LIN Transceiver with Voltage Regulator |
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| MCP2022P-330E/ST | 功能描述:LIN 收發(fā)器 LIN Transceiver with Vreg and LIN RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
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