參數(shù)資料
型號(hào)： MCP2050T-330E/SL
廠商： Microchip Technology
文件頁數(shù)： 41/42頁
文件大?。?/td> 0K
描述： IC TXRX LIN 3.3V LDO 14-SOIC
產(chǎn)品培訓(xùn)模塊： Microchip MCP20xx LIN Transceiver Overview
標(biāo)準(zhǔn)包裝： 2,600
系列： *
2012 Microchip Technology Inc.
DS22299B-page 8
MCP2050
If CS/LWAKE = 0, the device can work in POWER-
DOWN mode or READY mode.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-on Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 k) is used
to reduce current. When CS/LWAKE is ‘0’ a stronger
pull-down (~300 k) is used to maintain the logic level.
This pin may also be used as a local wake-up input
(see Figure 1-14). The microcontroller will set the I/O
pin to control the CS/LWAKE. An external switch, or
other source, can then wake-up both the transceiver
and the microcontroller.
1.3.8
FAULT/TXE
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV tolerant open drain (up to 30V).
The input section is identical with TXD section (TTL
level, HV compliant, adaptive pull-up). Internal
adaptive pull-up maintains this input high '1' if the pin is
floating. Its state is defined as shown in Table 1-3. The
device is placed in TRANSMITTER OFF mode
whenever this pin is LOW (‘0’), either from an internal
fault condition or by external drive.
If CS/LWAKE is HIGH (‘1”), the FAULT/TXE signals a
mismatch between the TXD input and the LBUS level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains LOW (‘0’)
(refer to Table 1-3).
The FAULT/TXE pin sampled at a rate faster than every
10 s.
1.3.9
RESET
RESET OUTPUT pin. This pin is open drain with
~90 k pull-up to VREG. It indicates the internal
voltage has reached a valid, stable level. As long as the
internal voltage is valid (above 0.8VREG), this pin will
remain HIGH (‘1’); otherwise the RESET pin switches
to LOW (‘0’).
1.3.10
WWDTRESET
WWDTRESET is an open-drain output pin. This pin is
asserted low when the internal Windowed Watchdog
Timer has expired or an attempt was made to clear the
timer before the window has opened.
1.3.11
WWDTTRIG
This is an input pin to reset the Windowed Watchdog
Timer. A high-to-low transition during the open window
time will reset the timer and prevent the WWDT from
timing out. The pin has an internal adaptive pull-up to
an internally-generated 4.2V (approximate.).
When WWDTTRIG is ‘0’, a weak pull-up (~800 k
is
connected
to reduce current.
When WWDTTRIG is ‘1’ the pull-up is stronger to
maintain the logic level.
Note:
CS/LWAKE should NOT be tied directly to
pin VREG as this could force the
MCP2050 into Operation Mode before the
microcontroller is initialized.
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