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參數(shù)資料
型號(hào)： MCP2150T-I/SS
廠商： Microchip Technology
文件頁(yè)數(shù)： 46/52頁(yè)
文件大小： 0K
描述： IC IRDA STD CONTROLLER 20SSOP
標(biāo)準(zhǔn)包裝： 1,600
控制器類(lèi)型： IRDA 標(biāo)準(zhǔn)協(xié)議?？刂破?br>
接口： UART
電源電壓： 3 V ~ 5.5 V
電流 - 電源： 7mA
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
配用： MCP215XDM-ND - BOARD DEMO FOR MCP215X
其它名稱(chēng)： MCP2150TI/SS
PIC16F193X/LF193X
DS41364D-page 50
Preliminary
2009 Microchip Technology Inc.
Banks 9-14
x00h/
x80h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
x00h/
x81h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
x02h/
x82h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
x03h/
x83h(2)
STATUS
—
—TO
PD
ZDC
C
---1 1000 ---q quuu
x04h/
x84h(2)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
x05h/
x85h(2)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
x06h/
x86h(2)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
x07h/
x87h(2)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
x08h/
x88h(2)
BSR
—
BSR<4:0>
---0 0000 ---0 0000
x09h/
x89h(2)
WREG
Working Register
0000 0000 uuuu uuuu
x0Ah/
x8Ah(1),(2)
PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
x0Bh/
x8Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—
Unimplemented
—
TABLE 3-14:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
4:
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
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