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| 型號(hào)： | MCP23008T-E/ML |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 40/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 20QFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 1.7MHz |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
| 包括： | POR |
| 配用： | GPIODM-KPLCD-ND - BOARD DEMO LCD GPIO EXP KEYPAD |
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2007 Microchip Technology Inc.
DS21919E-page 5
MCP23008/MCP23S08
1.0
DEVICE OVERVIEW
The MCP23X08 device provides 8-bit, general
purpose, parallel I/O expansion for I2C bus or SPI
applications. The two devices differ in the number of
hardware address pins and the serial interface:
MCP23008 – I2C interface; three address pins
MCP23S08 – SPI interface; two address pins
The MCP23X08 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
When
any
input
state
differs
from
its
corresponding input port register state, this is
used to indicate to the system master that an
input state has changed.
2.
When an input state differs from a preconfigured
register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
1.1
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTION
Pin
Name
PDIP/
SOIC
QFN
SSOP
Pin
Type
Function
SCL/SCK
1
19
1
I
Serial clock input.
SDA/SI
2
20
2
I/O
Serial data I/O (MCP23008)/Serial data input (MCP23S08).
A2/SO
3
1
3
I/O
Hardware address input (MCP23008)/
Serial data output (MCP23S08).
A2 must be biased externally.
A1
4
2
4
I
Hardware address input. Must be biased externally.
A0
5
3
5
I
Hardware address input. Must be biased externally.
RESET
6
4
6
I
External reset input. Must be biased externally.
NC/CS
7
5
7
I
No connect (MCP23008)/External chip select input (MCP23S08).
INT
8
7
8
O
Interrupt output. Can be configured for active-high, active-low or
open-drain.
VSS
9179
P
Ground.
GP0
10
9
12
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP1
11
10
13
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP2
12
11
14
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP3
13
12
15
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP4
14
13
16
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP5
15
14
17
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP6
16
15
18
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP7
17
16
19
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
VDD
18
20
P
Power.
N/C
—
6, 8
10, 11
—
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