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參數(shù)資料
| 型號(hào)： | MCP23009T-E/MG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PQCC16 |
| 封裝： | 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16 |
| 文件頁數(shù)： | 48/50頁 |
| 文件大?。?/td> | 607K |
| 代理商： | MCP23009T-E/MG |
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2009 Microchip Technology Inc.
DS22121B-page 7
MCP23009/MCP23S09
1.3.3
SPI INTERFACE
The MCP23S09 operates in Mode 0,0 and Mode 1,1.
The difference between the two modes is the idle state
of the clock.
Mode 0,0: The idle state of the clock is LOW. Input data
is latched on the rising edge of the clock; output data is
driven on the falling edge of the clock.
Mode 1,1: The idle state of the clock is HIGH. Input
data is latched on the rising edge of the clock; output
data is driven on the falling edge of the clock.
1.3.3.1
SPI Write Operation
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2
SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
1.3.3.3
SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer. (see Section 1.3.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
The sequence ends by the raising of CS.
The MCP23S09 address pointer will roll over to
address zero after reaching the last register address.
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