RXF13EIDL(6)
參數(shù)資料
型號： MCP2510-I/SO
廠商： Microchip Technology
文件頁數(shù)： 63/80頁
文件大?。?/td> 0K
描述： IC CAN CONTRLER IND TEMP 18SOIC
產(chǎn)品培訓模塊： CAN Bus Protection
標準包裝： 42
控制器類型： CAN 接口
接口： SPI
電源電壓： 3 V ~ 5.5 V
電流 - 電源： 10mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 18-SOIC
包裝： 管件
產(chǎn)品目錄頁面： 685 (CN2011-ZH PDF)
配用： DV251001-ND - KIT DEVELOPMENT CAN MCP2510
PIC18F2480/2580/4480/4580
DS39637D-page 66
2009 Microchip Technology Inc.
RXF13EIDL(6) 2480 2580 4480 4580
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RXF13EIDH(6) 2480 2580 4480 4580
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RXF13SIDL(6) 2480 2580 4480 4580
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RXF13SIDH(6) 2480 2580 4480 4580
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RXF12EIDL(6) 2480 2580 4480 4580
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RXF12EIDH(6) 2480 2580 4480 4580
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RXF12SIDL(6) 2480 2580 4480 4580
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RXF12SIDH(6) 2480 2580 4480 4580
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RXF11EIDL(6) 2480 2580 4480 4580
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RXF11EIDH(6) 2480 2580 4480 4580
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RXF11SIDL(6) 2480 2580 4480 4580
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RXF11SIDH(6) 2480 2580 4480 4580
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RXF10EIDL(6) 2480 2580 4480 4580
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RXF10EIDH(6) 2480 2580 4480 4580
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RXF10SIDL(6) 2480 2580 4480 4580
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RXF10SIDH(6) 2480 2580 4480 4580
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RXF9EIDL(6)
2480 2580 4480 4580
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RXF9EIDH(6)
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RXF9SIDL(6)
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RXF9SIDH(6)
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RXF8EIDL(6)
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RXF8EIDH(6)
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RXF8SIDL(6)
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RXF8SIDH(6)
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RXF7EIDL(6)
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RXF7EIDH(6)
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RXF7SIDL(6)
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RXF7SIDH(6)
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RXF6EIDL(6)
2480 2580 4480 4580
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RXF6EIDH(6)
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RXF6SIDL(6)
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RXF6SIDH(6)
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TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 5-3 for Reset value for specific condition.
5:
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6:
This register reads all ‘0’s until ECAN technology is set up in Mode 1 or Mode 2.
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