參數(shù)資料
型號： MCP2510T-I/ST
廠商： Microchip Technology
文件頁數(shù)： 33/80頁
文件大?。?/td> 0K
描述： IC CAN CONTROLLER W/SPI 20-TSSOP
標準包裝： 2,500
控制器類型： CAN 接口
接口： SPI
電源電壓： 3 V ~ 5.5 V
電流 - 電源： 10mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 20-TSSOP
包裝： 帶卷 (TR)
配用： DV251001-ND - KIT DEVELOPMENT CAN MCP2510
2007 Microchip Technology Inc.
DS21291F-page 39
MCP2510
5.10
Bit Timing Configuration
Registers
The configuration registers (CNF1, CNF2, CNF3) con-
trol the bit timing for the CAN bus interface. These reg-
isters can only be modified when the MCP2510 is in
configuration mode (see Section 9.0).
5.10.1
CNF1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of TQ relative to the OSC1
input frequency, with the minimum length of TQ being 2
OSC1 clock cycles in length (when BRP<5:0> are set
to 000000). The SJW<1:0> bits select the synchroni-
zation jump width in terms of number of TQ’s.
5.10.2
CNF2
The PRSEG<2:0> bits set the length, in TQ’s, of the
propagation segment. The PHSEG1<2:0> bits set the
length, in TQ’s, of phase segment 1. The SAM bit con-
trols how many times the RXCAN pin is sampled. Set-
ting this bit to a ‘1’ causes the bus to be sampled three
times; twice at TQ/2 before the sample point, and once
at the normal sample point (which is at the end of phase
segment 1). The value of the bus is determined to be
the value read during at least two of the samples. If the
SAM bit is set to a ‘0’ then the RXCAN pin is sampled
only once at the sample point. The BTLMODE bit con-
trols how the length of phase segment 2 is determined.
If this bit is set to a ‘1’ then the length of phase segment
2 is determined by the PHSEG2<2:0> bits of CNF3
(see Section 5.10.3). If the BTLMODE bit is set to a ‘0’
then the length of phase segment 2 is the greater of
phase segment 1 and the information processing time
(which is fixed at 2 TQ for the MCP2510).
5.10.3
CNF3
The PHSEG2<2:0> bits set the length, in TQ’s, of
Phase Segment 2, if the CNF2.BTLMODE bit is set to
a ‘1’. If the BTLMODE bit is set to a ‘0’ then the
PHSEG2<2:0> bits have no effect.
REGISTER 5-1:
CNF1 - CONFIGURATION REGISTER1 (ADDRESS: 2Ah)
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
bit 7-6
SJW<1:0>: Synchronization Jump Width Length
11
= Length = 4 x TQ
10
= Length = 3 x TQ
01
= Length = 2 x TQ
00
= Length = 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler
TQ = 2 x (BRP + 1) / FOSC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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