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參數(shù)資料
| 型號： | MCP3204-CIST |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI Serial Interface |
| 中文描述： | 2.7 4-Channel/8-Channel 12位A / D轉(zhuǎn)換器具有SPI串行接口 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 425K |
| 代理商： | MCP3204-CIST |
MCP3204/3208
DS21298B-page 16
Preliminary
1999 Microchip Technology Inc.
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Because communication with the MCP3204/3208
devices may not need multiples of eight clocks, it will be
necessary to provide more clocks than are required.
This is usually done by sending ‘leading zeros’ before
the start bit. As an example, Figure 6-1 and Figure 6-2
shows how the MCP3204/3208 can be interfaced to a
MCU with a hardware SPI port. Figure 6-1 depicts the
operation shown in SPI Mode 0,0 which requires that the
SCLK from the MCU idles in the ‘low’ state, while
Figure 6-2 shows the similar case of SPI Mode 1,1
where the clock idles in the ‘high’ state.
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains five leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Con-
verter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCUs receive buffer will contain three unknown bits
(the output is at high impedance for the first two clocks),
the null bit and the highest order four bits of the conver-
sion. After the third byte has been sent to the device, the
receive register will contain the lowest order eight bits of
the conversion results. Easier manipulation of the con-
verted data can be obtained by using this method.
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
D
IN
X = Don’t Care Bits
17
18
19
20
21
22
23
24
D
OUT
BIT
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HI-Z
MCU latches data from A/D Converter
Data is clocked out of
DO
Don’t Care
SGL/
D1
D2
Start
0
0
0
0
0
1
X
X
X
X
X
DO
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B3
B2
B1
B0
B11
B10
B9
B8
0
D1
D2
SGL/
Bit
(Null)
(Aligned with falling
edge of clock)
(Aligned with rising
edge of clock)
X
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
D
IN
X = Don’t Care Bits
17
18
19
20
21
22
23
24
D
OUT
DO
Don’t Care
BIT
B11
B10
B9
B8
B6
B5
B4
B3
B2
B1
B0
HI-Z
0
0
0
0
0
1
X
X
X
X
X
DO
SGL/
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B3
B2
B1
B0
B11
B10
B9
B8
MCU latches data from A/D Converter
Data is clocked out of
D1
D2
SGL/
Bit
(N0
D1
D2
Start
M(Aligned with falling
edge of clock)
(Aligned with rising
edge of clock)
B7
X
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
Data stored into MCU receive register
after transmission of last 8 bits
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