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| 鍨嬭櫉锛� | MCP3304-BI/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 34/48闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 13BIT 2.7V 4CH SPI 16DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 30 |
| 浣嶆暩(sh霉)锛� | 13 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 100k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 16-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-PDIP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 8 鍊嬪柈绔�锛屽柈妤碉紱4 鍊嬪樊鍒�锛屽柈妤� |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 672 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | MCP3304BI/P |
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MCP3302/04
DS21697F-page 4
2011 Microchip Technology Inc.
Analog Inputs
Full Scale Input Span
CH0 - CH7
-VREF
鈥擵REF
V
Absolute Input Voltage
CH0 - CH7
-0.3
鈥�
VDD + 0.3
V
Leakage Current
鈥�
0.001
卤1
A
Switch Resistance
RS
鈥�1
鈥�
k
See Figure 5-3
Sample Capacitor
CSAMPLE
鈥�
25
鈥�
pF
See Figure 5-3
Digital Input/Output
Data Coding Format
Binary Two鈥檚 Complement
High Level Input Voltage
VIH
0.7 VDD
鈥斺€�
V
Low Level Input Voltage
VIL
鈥�
0.3 VDD
V
High Level Output Voltage
VOH
4.1
鈥�
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
鈥斺€�
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
鈥�
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
鈥�
10
A
VOUT = VSS or VDD
Pin Capacitance
CIN, COUT
鈥�
10
pF
Timing Specifications:
Clock Frequency
(Note 8)
FCLK
0.105
鈥�
2.1
MHz
VDD = 5V, FSAMPLE = 100 ksps
Clock High Time
THI
210
鈥�
ns
Clock Low Time
TLO
210
鈥�
ns
CS Fall To First Rising CLK Edge
TSUCS
100
鈥�
ns
Data In Setup time
TSU
50
鈥�
ns
Data In Hold Time
THD
50
鈥�
ns
CLK Fall To Output Data Valid
TDO
鈥斺€�
125
ns
鈥�
200
ns
CLK Fall To Output Enable
TEN
鈥斺€�
125
ns
鈥�
200
ns
CS Rise To Output Disable
TDIS
鈥�
100
ns
See test circuits, Figure 1-2
CS Disable Time
TCSH
475
鈥�
ns
DOUT Rise Time
TR
鈥�
100
ns
See test circuits, Figure 1-2
DOUT Fall Time
TF
鈥�
100
ns
See test circuits, Figure 1-2
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TA = -40掳C to +85掳C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3: VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5V DC 卤500 mVP-P @ 1 kHz, see test circuit Figure 1-4.
5: Maximum clock frequency specification must be met.
6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25掳C and +85掳C.
8: For slow sample rates, see Section 5.2 鈥淒riving the Analog Input鈥� for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
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