V
參數(shù)資料
型號： MCP3304-CI/P
廠商： Microchip Technology
文件頁數(shù)： 23/48頁
文件大?。?/td> 0K
描述： IC ADC 13BIT 2.7V 4CH SPI 16-DIP
標準包裝： 30
位數(shù)： 13
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 16-DIP（0.300"，7.62mm）
供應商設(shè)備封裝： 16-PDIP
包裝： 管件
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
產(chǎn)品目錄頁面： 672 (CN2011-ZH PDF)
其它名稱： MCP3304CI/P
2011 Microchip Technology Inc.
DS21697F-page 3
MCP3302/04
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.3V to VDD +0.3V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Maximum Junction Temperature .................................. 150°C
ESD protection on all pins (HBM)
4kV
Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Conversion Rate
Maximum Sampling Frequency
FSAMPLE
—
100
ksps
See FCLK specification. Note 8
Conversion Time
TCONV
13
CLK
periods
Acquisition Time
TACQ
1.5
CLK
periods
DC Accuracy
Resolution
12 data bits + sign
bits
Integral Nonlinearity
INL
—
±0.5
±1
LSB
MCP3302/04-B
—
±1
±2
LSB
MCP3302/04-C
Differential Nonlinearity
DNL
—
±0.5
±1
LSB
Monotonic over temperature
Positive Gain Error
-3
-0.75
+2
LSB
Negative Gain Error
-3
-0.5
+2
LSB
Offset Error
-3
+3
+6
LSB
Dynamic Performance
Total Harmonic Distortion
THD
—
-91
—
dB
Signal-to-Noise and Distortion
SINAD
—
78
—
dB
Spurious Free Dynamic Range
SFDR
—
92
—
dB
Common Mode Rejection
CMRR
—
79
—
dB
Channel to Channel Crosstalk
CT
—
> -110
—
dB
Power Supply Rejection
PSR
—
74
—
dB
Reference Input
Voltage Range
0.4
—
VDD
V
Current Drain
—
100
150
A
—
0.001
3
A
CS = VDD = 5V
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to VREF level.
3: VIN = 0.1V to 4.9V @ 1 kHz.
4: VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4.
5: Maximum clock frequency specification must be met.
6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.
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