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| 型號： | MCP3421DM-BFG |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 23/42頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO FOR MCP3421 |
| 產(chǎn)品培訓(xùn)模塊： | MCP3901 Analog Front End |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電源管理，電池檢測計 |
| 已用 IC / 零件： | MCP3421 |
| 已供物品： | 板 |
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2009 Microchip Technology Inc.
DS22003E-page 3
MCP3421
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings
VDD...................................................................................7.0V
All inputs and outputs w.r.t VSS ............... –0.3V to VDD+0.3V
Differential Input Voltage ...................................... |VDD - VSS|
Output Short Circuit Current ................................ Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±10 mA
Storage Temperature ....................................-65°C to +150°C
Ambient Temp. with power applied ...............-55°C to +125°C
ESD protection on all pins
................ ≥ 6kVHBM, ≥ 400V MM
Maximum Junction Temperature (TJ). .........................+150°C
Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability
.
1.2
Electrical Specifications
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for T
A = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full scale range.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Analog Inputs
Differential Input Range
—
±2.048/PGA
—
V
VIN = VIN+ - VIN-
Common-Mode Voltage Range
(absolute)
VSS-0.3
—
VDD+0.3
V
Differential Input Impedance
ZIND (f)
—
2.25/PGA
—
M
Ω
During normal mode operation
Common Mode input
Impedance
ZINC (f)
—
25
—
M
Ω
PGA = 1, 2, 4, 8
System Performance
Resolution and No Missing
Codes
12
—
Bits
DR = 240 SPS
14
—
Bits
DR = 60 SPS
16
—
Bits
DR = 15 SPS
18
—
Bits
DR = 3.75 SPS
Data Rate
DR
176
240
328
SPS
S1,S0 = ‘00’, (12 bits mode)
44
60
82
SPS
S1,S0 = ‘01’, (14 bits mode)
11
15
20.5
SPS
S1,S0 = ‘10’, (16 bits mode)
2.75
3.75
5.1
SPS
S1,S0 = ‘11’, (18 bits mode)
Output Noise
—
1.5
—
VRMS
TA = +25°C, DR = 3.75 SPS,
PGA = 1, VIN = 0
Integral Nonlinearity (Note 4)
INL
—
10
35
ppm of
FSR
DR = 3.75 SPS
Internal Reference Voltage
VREF
—
2.048
—
V
Note 1:
Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2:
This input impedance is due to 3.2 pF internal input sampling capacitor.
3:
The total conversion speed includes auto-calibration of offset and gain.
4:
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
5:
Includes all errors from on-board PGA and VREF.
6:
Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.
7:
This parameter is ensured by characterization and not 100% tested.
8:
This parameter is ensured by design and not 100% tested.
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