High-Speed Mode (3.4 MHz): Not recommended for VDD
參數(shù)資料
型號: MCP3421DM-WS
廠商: Microchip Technology
文件頁數(shù): 18/42頁
文件大?。?/td> 0K
描述: BOARD DEMO MCP3421 WEIGHT SCALE
標(biāo)準(zhǔn)包裝: 1
主要目的: 參考設(shè)計,稱量臺
嵌入式: 是,MCU,8 位
已用 IC / 零件: MCP3421,MCP6V07,PIC18F4550
主要屬性: 2Kg測壓元件,靈敏度為1 mV/V
已供物品: 板,線纜,CD,電源
2009 Microchip Technology Inc.
DS22003E-page 25
MCP3421
High-Speed Mode (3.4 MHz): Not recommended for VDD < 2.7V
Clock frequency
fSCL
——
3.4
MHz
Cb = 100 pF
——
1.7
MHz
Cb = 400 pF
Clock high time
THIGH
60
ns
Cb = 100 pF, fSCL = 3.4 MHz
120
ns
Cb = 400 pF, fSCL = 1.7 MHz
Clock low time
TLOW
160
ns
Cb = 100 pF, fSCL = 3.4 MHz
320
ns
Cb = 400 pF, fSCL = 1.7 MHz
SCL rise time
TR
40
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
80
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SCL fall time
TF
40
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
80
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
SDA rise time
TR: DAT
80
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
160
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SDA fall time
TF: DATA
80
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
160
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
Data hold time
THD:DAT
0
70
ns
Cb = 100 pF, fSCL = 3.4 MHz
0—
150
ns
Cb = 400 pF, fSCL = 1.7 MHz
Output valid from clock
(Notes 2 and 3)
TAA
——
150
ns
Cb = 100 pF, fSCL = 3.4 MHz
——
310
ns
Cb = 400 pF, fSCL = 1.7 MHz
START condition hold time
THD:STA
160
ns
START (Repeated) condition
setup time
TSU:STA
160
ns
Data input setup time
TSU:DAT
10
ns
STOP condition setup time
TSU:STO
160
ns
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for T
A = -40 to +85°C,
VIN+ = VIN- = VREF/2, VSS = 0V, VDD = +2.7V to +5.0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold
Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the
bus line. If this parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than t
SP. If this parameter is too long, the Data Input Setup
(TSU:DAT) or Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
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