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| 鍨嬭櫉锛� | MCP3423-E/MF |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 20/58闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 18BIT 3.75SPS 2CH 10-DFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | MCP3901 Analog Front End |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 120 |
| 浣嶆暩(sh霉)锛� | 18 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 3.75 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | I²C锛屼覆琛� |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-VFDFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-DFN-EP锛�3x3锛� |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 4 鍊嬪柈绔�锛岄洐妤�锛�2 鍊嬪樊鍒�锛岄洐妤� |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 672 (CN2011-ZH PDF) |
| 閰嶇敤锛� | MCP3423EV-ND - BOARD EVAL 18BIT 2CH ADC MCP3423 |
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2009 Microchip Technology Inc.
DS22088C-page 27
MCP3422/3/4
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85掳C, VDD = +2.7V to +5.0V,
VSS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode (100 kHz)
Clock frequency
fSCL
0
鈥�
100
kHz
Clock high time
THIGH
4000
鈥�
ns
Clock low time
TLOW
4700
鈥�
ns
SDA and SCL rise time
鈥�
1000
ns
SDA and SCL fall time
TF
鈥�
300
ns
START condition hold time
THD:STA
4000
鈥�
ns
After this period, the first clock
pulse is generated.
START (Repeated) condition
setup time
TSU:STA
4700
鈥�
ns
Data hold time
THD:DAT
0
鈥�
3450
ns
Data input setup time
TSU:DAT
250
鈥�
ns
STOP condition setup time
TSU:STO
4000
鈥�
ns
Output valid from clock
TAA
0
鈥�
3750
ns
Bus free time
TBUF
4700
鈥�
ns
Time between START and STOP
conditions.
Fast Mode (400 kHz)
Clock frequency
TSCL
0
鈥�
400
kHz
Clock high time
THIGH
600
鈥�
ns
Clock low time
TLOW
1300
鈥�
ns
SDA and SCL rise time
TR
20 + 0.1Cb
鈥�
300
ns
SDA and SCL fall time
TF
20 + 0.1Cb
鈥�
300
ns
START condition hold time
THD:STA
600
鈥�
ns
After this period, the first clock
pulse is generated
START (Repeated) condition
setup time
TSU:STA
600
鈥�
ns
Data hold time
THD:DAT
0
鈥�
900
ns
Data input setup time
TSU:DAT
100
鈥�
ns
STOP condition setup time
TSU:STO
600
鈥�
ns
Output valid from clock
TAA
0
鈥�
1200
ns
Bus free time
TBUF
1300
鈥�
ns
Time between START and STOP
conditions.
Note
1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (T) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
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