參數(shù)資料
型號: MCP3550T-50E/MS
廠商: Microchip Technology
文件頁數(shù): 17/36頁
文件大小: 0K
描述: IC ADC 22BIT 2.7V 1CH 8MSOP
產(chǎn)品培訓模塊: MCP3901 Analog Front End
標準包裝: 2,500
位數(shù): 22
采樣率(每秒): 12.5
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
配用: MCP355XDV-MS1-ND - BOARD DEV SENSOR APP MCP355X
MCP355XDM-TAS-ND - BOARD DEMO TINY APP SNSR MCP355X
MCP3550/1/3
DS21950E-page 24
2009 Microchip Technology Inc.
5.4.1
READY FUNCTION OF SDO/RDY
PIN IN CONTINUOUS CONVERSION
MODE
The device enters Continuous Conversion mode if no
rising edge of CS is seen during tCONV and
consecutive conversions ensue. SDO/RDY will be
high, indicating that a conversion is in process. When
a conversion is complete, SDO/RDY will change to a
Low state. With the Low state of SDO/RDY after this
first conversion, the conversion data can be accessed
with the combination of SCK and SDO/RDY. If the data
ready event happens during the clocking out of the
data, the data ready bit will be displayed after the
complete 24-bit word communication (i.e., the data
ready event will not interrupt a data transfer).
If 24 bits of data are required from this conversion, they
must be accessed during this communication. You can
terminate data transition by bringing CS high, but the
remaining data will be lost and the converter will go into
Shutdown mode. Once the data has been transmitted
by the converter, the SDO/RDY pin will remain in the
LSB state until the 25th falling edge of SCK. At this
point, SDO/RDY is released from the Data Acquisition
mode and changed to the RDY state.
5.4.2
2-WIRE CONTINUOUS
CONVERSION OPERATION,
(CS TIED PERMANENTLY LOW)
It is possible to use only two wires to communicate with
the MCP3550/1/3 devices. In this state, the device is
always in Continuous Conversion mode, with internal
conversions continuously occurring. This mode can be
entered by having CS low during power-up or changing
it to a low position after power-up. If CS is low at power-
up, the first conversion of the converter is initiated
approximately 300 s after the power supply has
stabilized.
Note:
The RDY state is not latched to CS in this
mode; the RDY flag dynamically updates
on the SDO/RDY pin and remains in this
state until data is clocked out using the
SCK pin.
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