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| 型號： | MCP4011-103E/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 38/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 10K 1CH 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 2 線串行（芯片選擇，增/減） |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 674 (CN2011-ZH PDF) |
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2006 Microchip Technology Inc.
DS21978C-page 43
MCP4011/2/3/4
7.0
DESIGN CONSIDERATIONS
In the design of a system with the MCP401X devices,
the following considerations should be taken into
account:
The Power Supply
The Layout
7.1
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 7-1:
Typical Microcontroller
Connections.
7.2
Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4011/2/3/4’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
VDD
VSS
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0.1 F
PIC
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U/D
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