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參數(shù)資料
| 型號(hào)： | MCP4017T-502E/LT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 27/51頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 5K 128TAPS SC70-6 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 128 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | SC-70-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 674 (CN2011-ZH PDF) |
| 其它名稱： | MCP4017T-502E/LTDKR |
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2009 Microchip Technology Inc.
DS22147A-page 33
MCP4017/18/19
5.0
SERIAL INTERFACE -
I2C MODULE
A 2-wire I2C serial protocol is used to write or read the
digital potentiometer’s wiper register. The I2C protocol
utilizes the SCL input pin and SDA input/output pin.
The I2C serial interface supports the following features.
Slave mode of operation
7-bit addressing
The following clock rate modes are supported:
- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s
Support Multi-Master Applications
The serial clock is generated by the Master.
The I2C Module is compatible with the Phillips I2C
specification. Phillips only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
for the MCP4017, MCP4018, and MCP4019 devices
are defined in this section of the Data Sheet.
FIGURE 5-1:
Typical Application I2C Bus
Configurations.
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
5.1
I2C I/O Considerations
I2C specifications require active low, passive high
functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to VSS (common) with a pull-up resistor. The
specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts the pull-up value for optimum system
performance.
Common pull-up values range from 1 kΩ to a max of
~10 kΩ. Power sensitive applications tend to choose
higher values to minimize current losses during
communication but these applications also typically
utilize lower VDD.
The SDA and SCL float (are not driving) when the
device is powered down.
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.
5.1.1
SLOPE CONTROL
The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
Single I2C Bus Configuration
Host
Controller
Device 1
Device 3
Device n
Device 2
Device 4
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