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| 型號： | MCP40D17T-103E/LT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 36/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 10K 128TAPS SC70-6 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 128 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | SC-70-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 674 (CN2011-ZH PDF) |
| 其它名稱： | MCP40D17T-103E/LTDKR |
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2009 Microchip Technology Inc.
DS22152B-page 41
MCP40D17/18/19
6.0
RESISTOR NETWORK
The Resistor Network is made up of two parts. These
are:
Resistor Ladder
Wiper
Figure 6-1 shows a block diagram for the resistive
network.
Digital potentiometer applications can be divided into
two resistor network categories:
Rheostat configuration
Potentiometer (or voltage divider) configuration
The MCP40D17 is a true rheostat, with terminal B and
the wiper (W) of the variable resistor available on pins.
The MCP40D18 device offers a voltage divider
(potentiometer) with terminal B internally connected to
ground.
The MCP40D19 device is a Rheostat device with
terminal A of the resistor floating, terminal B internally
connected to ground, and the wiper (W) available on
pin.
6.1
Resistor Ladder Module
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the
series (ladder)
determines
the
RAB
resistance
(see Figure 6-1). The end points of the resistor ladder
are connected to the device Terminal A and Terminal B
pins. The RAB (and RS) resistance has small variations
over voltage and temperature.
The Resistor Network has 127 resistors in a string
between terminal A and terminal B. This gives 7-bits of
resolution.
The wiper can be set to tap onto any of these 127
resistors
thus
providing
128
possible
settings
(including terminal A and terminal B). This allows zero
scale to full scale connections.
A wiper setting of 00h connects the Terminal W (wiper)
to Terminal B (Zero Scale). A wiper setting of 3Fh is the
Mid scale setting. A wiper setting of 7Fh connects
the Terminal W (wiper) to Terminal A (Full Scale).
Table 6-1 illustrates the full wiper setting map.
Terminal A and B as well as the wiper W do not have a
polarity. These terminals can support both positive and
negative current.
FIGURE 6-1:
Resistor Network Block
Diagram.
TABLE 6-1:
WIPER SETTING MAP
Wiper Setting
Properties
07Fh
Full Scale (W = A)
07Eh - 040h
W = N
03Fh
W = N (Mid Scale)
03Eh - 001h
W = N
000h
Zero Scale (W = B)
RS
A
RS
B
N = 127
N = 126
N = 125
N = 1
N = 0
RW (1)
W
01h
Analog
Mux
RW (1)
00h
RW (1)
7Dh
RW (1)
7Eh
RW (1)
7Fh
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation has
more effect on devices with smaller RAB
resistance (5.0 k
Ω).
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| MCP40D17T-104AE/LT | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:7-Bit Single I2C? (with Command Code) Digital POT with Volatile Memory in SC70 |
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