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| 型號(hào)： | MCP41100T-I/SN |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 15/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIGITL 100K 1CH SPI 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 800 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | 3 線串行（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
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MCP41XXX/42XXX
DS11195C-page 22
2003 Microchip Technology Inc.
5.8
Using the MCP41XXX/42XXX in
SPI Mode 1,1
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
FIGURE 5-5:
Timing Diagram for SPI Mode 1,1 Operation.
SO
SI
SCK
CS
23
456
7
8
9
10
1
New Register Data
D7
D6
D5
D4
D3
D2
D1
D0
P1* P0
11
12
13
14
15
16
X
C1
C0
X
Channel
Select
Bits
Data Registers are
loaded on rising
edge of CS. Shift
First 16 bits Shifted out will always be zeros
Don’t
Care
Bits
Command
Bits
Don’t
Care
Bits
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
COMMAND BYTE
DATA BYTE
X
register is loaded
with zeros at this time.
Data is always latched in
on the rising edge of SCK.
Data is always clocked out the SO
pin after the falling edge of SCK.
SO pin will always
drive low when CS
goes high.
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