參數(shù)資料
型號: MCP4241T-502E/SL
廠商: Microchip Technology
文件頁數(shù): 37/88頁
文件大小: 0K
描述: IC DGTL POT 5K 2CH 14SOIC
標準包裝: 2,600
系列: WiperLock™
接片: 129
電阻(歐姆): 5k
電路數(shù): 2
溫度系數(shù): 標準值 150 ppm/°C
存儲器類型: 非易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 帶卷 (TR)
其它名稱: MCP4241T-502E/SLTR
MCP414X/416X/424X/426X
DS22059B-page 42
2008 Microchip Technology Inc.
6.2
The SPI Modes
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.2.1
MODE 0,0
In Mode 0,0: SCK idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
6.2.2
MODE 1,1
In Mode 1,1: SCK idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
6.3
SPI Waveforms
Figure 6-3 through Figure 6-8 show the different SPI
command waveforms. Figure 6-3 and Figure 6-4 are
read and write commands. Figure 6-5 and Figure 6-6
are read commands when the SDI and SDO pins are
multiplexed on the same pin (SDI/SDO). Figure 6-7
are
increment and decrement
commands. The high voltage increment and decrement
commands are used to enable and disable WiperLock
Technology and Write Protect.
FIGURE 6-3:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
FIGURE 6-4:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
CS
SCK
Write to
SSPBUF
SDI
Input
Sample
SDO
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15 bit14 bit13 bit12
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AD3 AD2 AD1
AD0
C1
C0
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
VIH
VIL
CMDERR bit
VIHH
CS
SCK
Write to
SSPBUF
SDI
Input
Sample
SDO
bit15
bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15 bit14 bit13 bit12
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AD3 AD2 AD1
AD0
C1
C0
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
VIH
VIL
CMDERR bit
VIHH
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