參數(shù)資料
型號： MCP4241T-502E/ST
廠商： Microchip Technology
文件頁數(shù)： 44/88頁
文件大?。?/td> 0K
描述： IC DGTL POT 5K 2CH 14TSSOP
標準包裝： 2,500
系列： WiperLock™
接片： 129
電阻（歐姆）： 5k
電路數(shù)： 2
溫度系數(shù)： 標準值 150 ppm/°C
存儲器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 14-TSSOP
包裝： 帶卷 (TR)
其它名稱： MCP4241T-502E/STTR
2008 Microchip Technology Inc.
DS22059B-page 49
MCP414X/416X/424X/426X
7.5
Write Data
Normal and High Voltage
The Write command is a 16-bit command. The Write
Command can be issued to both the Volatile and
Non-Volatile memory locations. The format of the
command is shown in Figure 7-2.
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command (16-clock) have been received.
A Write command to a Non-Volatile memory location
will only start a write cycle after a properly formatted
Write Command (16-clock) have been received and the
CS pin transitions to the inactive state (VIH).
7.5.1
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Write Command (Command Byte and
Data Byte) is then clocked in on the SCK and SDI pins.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses. This
protects against system issues from corrupting the
Non-Volatile memory locations.
Figure 6-3 and Figure 6-4 show possible waveforms
for a single write.
7.5.2
SINGLE WRITE TO NON-VOLATILE
MEMORY
The sequence to write to to a single non-volatile
memory location is the same as a single write to volatile
memory with the exception that after the CS pin is
driven inactive (VIH), the EEPROM write cycle (tWC) is
started. A write cycle will not start if the write command
isn’t exactly 16 clocks pulses. This protects against
system issues from corrupting the Non-Volatile
memory locations.
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving the
CS pin to the active state (VILor VIHH).
During an EEPROM write cycle, only serial commands
to Volatile memory (addresses 00h, 01h, 04h, and 05h)
are accepted. All other serial commands are ignored
until the EEPROM write cycle (twc) completes. This
allows the Host Controller to operate on the Volatile
Wiper registers and the TCON register, and to Read
the Status Register. The EEWA bit in the Status register
indicates the status of an EEPROM Write Cycle.
Once a write command to a Non-Volatile memory
location has been received, NO other SPI commands
should be received before the CS pin transitions to the
inactive state (VIH) or the current SPI command will
have a Command Error (CMDERR) occur.
FIGURE 7-2:
Write Command - SDI and SDO States.
Note:
Writes to certain memory locations will be
dependant on the state of the WiperLock
Technology bits and the Write Protect bit.
A
D
3
A
D
2
A
D
1
A
D
0
00
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1111111111111111 Valid Address/Command combination
111111
0
0 Invalid Address/Command combination (1)
COMMAND BYTE
DATA BYTE
SDI
SDO
Note 1:
If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
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