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| 型號： | MCP4242T-503E/UN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 21/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RHEOSTAT 50K 2CH 10MSOP |
| 標準包裝： | 2,500 |
| 系列： | WiperLock™ |
| 接片： | 129 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MCP4242T-503-E/UN MCP4242T-503-E/UNTR MCP4242T-503-E/UNTR-ND MCP4242T-503E/UNTR |
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MCP414X/416X/424X/426X
DS22059B-page 28
2008 Microchip Technology Inc.
3.1
Chip Select (CS)
The CS pin is the serial interface’s chip select input.
Forcing the CS pin to VIL enables the serial commands.
Forcing the CS pin to VIHH enables the high-voltage
serial commands.
3.2
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin.
This pin is connected to the Host Controllers SDO pin.
3.3
Serial Data In / Serial Data Out
(SDI/SDO)
On the MCP41X1 devices, pin-out limitations do not
allow for individual SDI and SDO pins. On these
devices, the SDI and SDO pins are multiplexed.
The MCP41X1 serial interface knows when the pin
needs to change from being an input (SDI) to being an
output (SDO). The Host Controller’s SDO pin must be
properly protected from a drive conflict.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal potenti-
ometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital potentiome-
ter. This corresponds to a wiper value of 0x00 for both
7-bit and 8-bit devices.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
MCP42XX devices have two terminal B pins, one for
each resistor network.
3.6
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potenti-
ometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
terminal W must be between VSS and VDD.
MCP42XX devices have two terminal W pins, one for
each resistor network.
3.7
Potentiometer Terminal A
The terminal A pin is available on the MCP4XX1
devices, and is connected to the internal potentiome-
ter’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x100 for 8-bit devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP4XX2
devices, and the internally terminal A signal is floating.
MCP42X1 devices have two terminal A pins, one for
each resistor network.
3.8
Write Protect (WP)
The WP pin is used to force the non-volatile memory to
be write protected.
3.9
Shutdown (SHDN)
The SHDN pin is used to force the resistor network
terminals into the hardware shutdown state.
3.10
Serial Data Out (SDO)
The SDO pin is the serial interfaces Serial Data Out pin.
This pin is connected to the Host Controllers SDI pin.
This pin allows the Host Controller to read the digital
potentiometers registers, or monitor the state of the
command error bit.
3.11
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
3.12
No Connection (NC)
Those pins should be either connected to VDD or VSS.
3.13
Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
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