SPI Timing Waveform (Mode = 00
參數(shù)資料
型號(hào): MCP4341T-502E/ST
廠商: Microchip Technology
文件頁數(shù): 6/59頁
文件大小: 0K
描述: IC DGTL POT QUAD 5K 20TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: WiperLock™
接片: 129
電阻(歐姆): 5k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
MCP434X/436X
DS22233A-page 14
2009 Microchip Technology Inc.
FIGURE 1-3:
SPI Timing Waveform (Mode = 00).
TABLE 1-3:
SPI REQUIREMENTS (MODE = 00)
#
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—10
MHz
VDD = 2.7V to 5.5V
—1
MHz
VDD = 1.8V to 2.7V
70
CS Active (VIL or VIHH) to SCK↑ input
TcsA2scH
60
ns
71
SCK input high time
TscH
45
ns
VDD = 2.7V to 5.5V
500
ns
VDD = 1.8V to 2.7V
72
SCK input low time
TscL
45
ns
VDD = 2.7V to 5.5V
500
ns
VDD = 1.8V to 2.7V
73
Setup time of SDI input to SCK
↑ edge
TDIV2scH
10
ns
74
Hold time of SDI input from SCK
↑ edge
TscH2DIL20
ns
77
CS Inactive (VIH) to SDO output hi-impedance
TcsH2DOZ—
50
ns
80
SDO data output valid after SCK
↓ edge
TscL2DOV—
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
82
SDO data output valid after
CS Active (VIL or VIHH)
TssL2doV
85
ns
83
CS Inactive (VIH) after SCK↓ edge
TscH2csI
100
ns
VDD = 2.7V to 5.5V
1ms
VDD = 1.8V to 2.7V
84
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
ns
Note 1:
This specification by design.
CS
SCK
SDO
SDI
70
71
72
82
SDI
74
75, 76
MSb
BIT6 - - - - - -1
LSb
77
MSb IN
BIT6 - - - -1
LSb IN
80
83
84
73
VIH
VIL
VIHH
VIH
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