參數(shù)資料
型號： MCP4441T-103E/ML
廠商： Microchip Technology
文件頁數(shù)： 77/100頁
文件大小： 0K
描述： IC DGTL POT 129TAPS QUAD 20QFN
標(biāo)準(zhǔn)包裝： 3,300
接片： 129
電阻（歐姆）： 10k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
MCP444X/446X
DS22265A-page 78
2010 Microchip Technology Inc.
8.6
Design Considerations
In the design of a system with the MCP44XX devices,
the following considerations should be taken into
account:
8.6.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-8 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 8-8:
Typical Microcontroller
Connections.
8.6.2
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
8.6.2.1
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP44XX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is
capable
of
providing.
Particularly
harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.6.2.2
Footprint Compatibility
The specification of the MCP44XX pinouts was done to
allow systems to be designed to easily support the use
of either the dual (MCP46XX) or quad (MCP44XX)
device.
Figure 8-9 shows how the dual pinout devices fit on the
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
FIGURE 8-9:
Quad Pinout (TSSOP
Package) vs. Dual Pinout.
VDD
VSS
MCP
4
X/
446
X
0.1 F
PIC
TM
M
ic
ro
c
ont
ro
ller
0.1 F
SCL
HVC/A0
W
B
A
SDA
A1
1
2
3
4
17
18
19
20
RESET
A1
WP
VDD
MCP44X1
Quad Potentiometers
TSSOP
5
6
7
14
15
16
P0W
P0B
P0A
P1A
P1W
P1B
VSS
HVC/A0
SDA
SCL
MCP44X2
Quad Rheostat
1
2
3
4
11
12
13
14
P0B
A1
P0W
VDD
TSSOP
5
6
7
8
9
10
P2W
P1W
P2B
P3B
P3W
P1B
VSS
HVC/A0
SDA
SCL
8
9
10
P3B
P3W
P3A
12
P2W
P2A
P2B
11
MCP42X1 Pinout (1)
MCP42X2 Pinout
Note 1:
Pin 15 (RESET) is the Address A2 (A2)
pin on the MCP46x1 device.
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