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| 型號： | MCP4662T-503E/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 30/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 50K 256TAPS 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 257 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-VFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN-EP（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 677 (CN2011-ZH PDF) |
| 其它名稱： | MCP4662T-503E/MFDKR |
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MCP454X/456X/464X/466X
DS22107A-page 36
2008 Microchip Technology Inc.
3.1
High Voltage Command / Address 0
(HVC/A0)
The HVC/A0 pin is the Address 0 input for the I2C
interface as well as the High Voltage Command pin. At
the device’s POR/BOR the value of the A0 address bit
is latched. This input along with the A2 and A1 pins
completes the device address. This allows up to 8
MCP45xx/46xx devices can be on a single I2C bus.
During normal operation the the voltage on this pin
determines if the I2C command is a normal command
or a High Voltage command (when HVC/A0 = VIHH).
3.2
Serial Clock (SCL)
The SCL pin is the serial interfaces Serial Clock pin.
This pin is connected to the Host Controllers SCL pin.
The MCP45XX/46XX is a slave device, so it’s SCL pin
accepts only external clock signals.
3.3
Serial Data (SDA)
The SDA pin is the serial interfaces Serial Data pin.
This pin is connected to the Host Controllers SDA pin.
The SDA pin is an open-drain N-channel driver.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital potentiome-
ter. This corresponds to a wiper value of 0x00 for both
7-bit and 8-bit devices.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
MCP46XX devices have two terminal B pins, one for
each resistor network.
3.6
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potenti-
ometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
terminal W must be between VSS and VDD.
MCP46XX devices have two terminal W pins, one for
each resistor network.
3.7
Potentiometer Terminal A
The terminal A pin is available on the MCP4XX1
devices, and is connected to the internal potentiome-
ter’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full-Scale wiper value of the digital potentiome-
ter. This corresponds to a wiper value of 0x100 for 8-bit
devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP4XX2
devices, and the internally terminal A signal is floating.
MCP46X1 devices have two terminal A pins, one for
each resistor network.
3.8
Write Protect (WP)
The WP pin is used to force the non-volatile memory to
be write protected.
3.9
Address 2 (A2)
The A2 pin is the I2C interface’s Address 2 pin. Along
with the A1 and A0 pins, up to 8 MCP45XX/46XX
devices can be on a single I2C bus.
3.10
Address 1 (A1)
The A2 pin is the I2C interface’s Address 1 pin. Along
with the A2 and A0 pins, up to 8 MCP45XX/46XX
devices can be on a single I2C bus.
3.11
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
3.12
No Connect (NC)
These pins should be either connected to VDD or VSS.
3.13
Exposed Pad (EP)
This pad is conductively connected to the device’s sub-
strate. This pad should be tied to the same potential as
the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when con-
nected to a PCB heat sink.
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