f
參數(shù)資料
型號: MCP4921-E/P
廠商: Microchip Technology
文件頁數(shù): 21/22頁
文件大小: 0K
描述: IC DAC 12BIT SNGL W/SPI 8DIP
標(biāo)準(zhǔn)包裝: 60
設(shè)置時(shí)間: 4.5µs
位數(shù): 12
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 673 (CN2011-ZH PDF)
SY69952
7
Micrel, Inc.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
Symbol
Parameter
Min.
Typ.
Max.
Units
Condition
fREF
Reference Frequency
6.41
6.48
6.55
MHz
MODE = 0
19.24
19.44
19.64
MHZ
MODE = 1
fB
Bit Time(1)
19.5
19.3
19.1
ns
MODE = 0
6.50
6.43
6.36
ns
MODE = 1
tODC
Output Duty Cycle(2)
48
52
%
(TCLK±, RCLK±)
tRF
ECL Output Rise/Fall Tiime(2)
0.4
1.2
ns
5pf load, 50
to VCC –2 (20% to 80%)
tLOCK
PLL Lock Time(2)
1
s
RIN transition density 25%
tRPWH
REFCLK Pulse Width High
3.3
ns
MODE = 0
10
ns
MODE = 1
tRPWL
REFCLK Pulse Width Low
3.3
ns
MODE = 0
10
ns
MODE = 1
tDV
Data Valid
3
ns
Prior to RCLK+ rising edge
tDH
Data Hold
1
ns
After RCLK+ rising edge
tPD
Propagation Delay(3)
——
10
ns
(RIN to ROUT, TSER to TOUT)
VCC = +5V ±5%; VEE = GND = 0V, TA = 0°C to +85°C
AC ELECTRICAL CHARACTERISTICS
NOTES:
1. fB is calculated as 1/(fREF * 8).
2. Tested initially and after any design or process changes that may affect these parameters.
3. The ECL switching threshold is the differential zero crossing (ie, the point where + and – signals cross).
TIMING WAVEFORMS
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