- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3434 > MCP601-E/P (Microchip Technology)IC OPAMP CMOS SGL 2.7V 8-DIP PDF資料下載
參數(shù)資料
| 型號： | MCP601-E/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 5/34頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CMOS SGL 2.7V 8-DIP |
| 標準包裝： | 60 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 2.3 V/µs |
| 增益帶寬積： | 2.8MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 700µV |
| 電流 - 電源： | 230µA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 678 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
2007 Microchip Technology Inc.
DS21314G-page 13
MCP601/1R/2/3/4
4.2
Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP601/1R/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 k
Ω load to V
DD/2. Figure 2-33
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Swing. This specification defines the maximum
output swing that can be achieved while the amplifier is
still operating in its linear region. To verify linear
operation in this range, the large signal (DC Open-Loop
Gain (AOL)) is measured at points 100 mV inside the
supply rails. The measurement must exceed the
specified gains in the specification table.
4.3
MCP603 Chip Select
The MCP603 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to -0.7 A (typ.), which is pulled through the CS pin to
VSS. When this happens, the amplifier output is put into
a high-impedance state. Pulling CS low enables the
amplifier.
The CS pin has an internal 5 M
Ω (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 is the Chip Select timing
diagram and shows the output voltage, supply currents,
and CS current in response to a CS pulse. Figure 2-27
shows the measured output voltage response to a CS
pulse.
4.4
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 40 pF when G = +1), a small series
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-4:
Output resistor RISO
stabilizes large capacitive loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN) in order to make
it easier to interpret the plot for arbitrary gains. GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN = 1 + |Gain|
(e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5:
Recommended RISO values
for capacitive loads.
Once you have selected RISO for your circuit, double-
check the resulting frequency response peaking and
step response overshoot in your circuit. Evaluation on
the bench and simulations with the MCP601/1R/2/3/4
SPICE macro model are very helpful. Modify RISO’s
value until the response is reasonable.
4.5
Supply Bypass
With this family of op amps, the power supply pin (VDD
for single-supply) should have a local bypass capacitor
(i.e., 0.01 F to 0.1 F) within 2 mm for good high-
frequency performance. It also needs a bulk capacitor
(i.e., 1 F or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
nearby analog parts.
MCP60X
RISO
VOUT
CL
RF
RG
+
–
Normalized Load Capacitance;
CL / G(F)
R
e
commended
R
IS
O
(
)
10p
100p
1n
10n
10
100
1k
GN = +1
GN ≥ +2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 78207-120 | FRICTION LATCH HEADER DR R/A |
| 1-1761685-0 | IDC LOW PRO HDR 30P VERT SHT LAT |
| 3793-6003 | CONN HEADER 10POS STR NO LATCH |
| LT1114ACN#PBF | IC PREC OP-AMP LOWPWR QUAD 14DIP |
| LT1114ACN | IC PREC OP-AMP LOWPWR QUAD 14DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCP601-ESL | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 6.0V Single Supply CMOS Op Amps |
| MCP601-ESN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 6.0V Single Supply CMOS Op Amps |
| MCP601-EST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 6.0V Single Supply CMOS Op Amps |
| MCP601-I | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 5.5V Single Supply CMOS Op Amps |
| MCP601-I/CH | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2.7V to 5.5V Single-Supply CMOS Op Amps |
發(fā)布緊急采購，3分鐘左右您將得到回復。