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參數資料
| 型號： | MCP6023-I/SN |
| 廠商： | Microchip Technology |
| 文件頁數： | 10/42頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP 2.5V R-R I/O 8SOIC |
| 標準包裝： | 100 |
| 放大器類型： | 通用 |
| 電路數： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 7 V/µs |
| 增益帶寬積： | 10MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 1mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產品目錄頁面： | 679 (CN2011-ZH PDF) |
| 其它名稱： | MCP6023I/SN |
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MCP6021/1R/2/3/4
DS21685D-page 18
2009 Microchip Technology Inc.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
FIGURE 4-3:
Output Resistor RISO
Stabilizes Large Capacitive Loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-4:
Recommended RISO values
for capacitive loads.
After selecting RISO for your circuit, double-check the
resulting
frequency
response
peaking
and
step
response overshoot. Modify RISO’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.4
Gain Peaking
(frequency
response)
gain
peaking
and
(step
response) overshoot. The capacitance to ground at the
inverting input (CG) is the op amp’s common mode
input capacitance plus board parasitic capacitance. CG
is in parallel with RG, which causes an increase in gain
at high frequencies for non-inverting gains greater than
1 V/V (unity gain). CG also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
FIGURE 4-5:
Non-inverting Gain Circuit
with Parasitic Capacitance.
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
FIGURE 4-6:
Non-inverting gain circuit
with parasitic capacitance.
4.5
MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is pulled high, the supply current drops
to 10 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M
Ω (typical)
pulldown resistor connected to VSS, so it will go low if
the CS pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS pulse.
VIN
MCP602X
RISO
VOUT
CL
10
100
1,000
10
100
1,000
10,000
Normalized Capacitance; CL/GN (pF)
Recommended
R
IS
O
(
Ω
)
GN ≥ +1
VIN
RG
RF
VOUT
CG
1.E+02
1.E+03
1.E+04
1.E+05
110
Noise Gain; GN (V/V)
Maximum
R
F
(
Ω
)
GN > +1 V/V
100
1k
10k
100k
CG = 7 pF
CG = 20 pF
CG = 50 pF
CG = 100 pF
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