2007 Microchip Technology Inc.
DS21314G-page 7
MCP601/1R/2/3/4
Note: Unless otherwise indicated, T
A = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-13:
Channel-to-Channel
Separation vs. Frequency.
FIGURE 2-14:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15:
DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-16:
CMRR, PSRR vs.
Frequency.
FIGURE 2-17:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
FIGURE 2-18:
DC Open-Loop Gain vs.
Supply Voltage.
90
100
110
120
130
140
150
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Channel-
to-
C
hannel
S
e
paration
(
d
B)
No Load
Input Referred
1k
10k
100k
1M
1
10
100
1000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input
Bias
and
Off
set
Currents
(pA)
IB
VDD = 5.5V
VCM = 4.3V
IOS
80
90
100
110
120
1.E+02
1.E+03
1.E+04
1.E+05
Load Resistance ()
D
C
Open-Loop
Gain
(
d
B
)
VDD = 2.7V
VDD = 5.5V
100
1k
10k
100k
10
20
30
40
50
60
70
80
90
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR,
PSRR
(
d
B)
CMRR
VDD = 5.0V
1100
10k
1M
PSRR+
PSRR–
10
1k
100k
1
10
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input
Bias
and
Off
set
Currents
(pA)
IB, +85°C
VDD = 5.5V
max. VCMR ≥ 4.3V
IB, +125°C
IOS, +85°C
IOS, +125°C
80
90
100
110
120
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power Supply Voltage (V)
DC
Open-Loop
Gain
(dB)
RL = 25 k