參數(shù)資料
型號(hào)： MCP606T-I/SN
廠商： Microchip Technology
文件頁數(shù)： 7/42頁
文件大?。?/td> 0K
描述： IC OPAMP 2.5V R-R 8SOIC
標(biāo)準(zhǔn)包裝： 3,300
放大器類型： 通用
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 0.08 V/µs
增益帶寬積： 155kHz
電流 - 輸入偏壓： 1pA
電壓 - 輸入偏移： 250µV
電流 - 電源： 18.7µA
電流 - 輸出 / 通道： 17mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 帶卷 (TR)
2009 Microchip Technology Inc.
DS11177F-page 15
MCP606/7/8/9
4.0
APPLICATIONS INFORMATION
The MCP606/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
4.1
Rail-to-Rail Inputs
4.1.1
PHASE REVERSAL
The MCP606/7/8/9 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages.
shows
the
input
voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings at the beginning of
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.3
NORMAL OPERATION
The input stage of the MCP606/7/8/9 op amps use a
PMOS input stage. It operates at low common mode
input voltage (VCM), including ground. WIth this
topology, the device operates with VCM up to VDD –1.1V
and 0.3V below VSS.
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
FIGURE 4-3:
Unity Gain Buffer has a
Limited VOUT Range.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN–
V1
R1
VDD
D1
R1 >
VSS – (minimum expected V1)
2mA
R2 >
VSS – (minimum expected V2)
2mA
V2
R2
D2
R3
MCP60X
VOUT
+
–
VIN
MCP60X
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