The analog output pins (V
參數(shù)資料
型號： MCP623T-E/CHY
廠商： Microchip Technology
文件頁數(shù)： 15/66頁
文件大?。?/td> 0K
描述： IC OPAMP SGL 2.5MA 20MHZ SOT23-6
標準包裝： 1
系列： mCal 技術
放大器類型： 通用
電路數(shù)： 1
輸出類型： 滿擺幅
轉換速率： 10 V/µs
增益帶寬積： 20MHz
電流 - 輸入偏壓： 5pA
電壓 - 輸入偏移： 200µV
電流 - 電源： 2.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應商設備封裝： SOT-23-6
包裝： 標準包裝
其它名稱： MCP623T-E/CHYDKR
MCP621/1S/2/3/4/5/9
DS22188C-page 22
2009-2011 Microchip Technology Inc.
3.1
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4
Calibration Common Mode
Voltage Input
A low-impedance voltage placed at this input (VCAL)
will set the op amps’ Common mode input voltage
during calibration. If this pin is left open, the Common
mode input voltage during calibration is approximately
VDD/3. The internal resistor divider is disconnected
from the supplies whenever the part is not in
calibration.
3.5
Calibrate/Chip Select Digital Input
This input (CAL/CS, …) is a CMOS, Schmitt-triggered
input that affects the calibration and Low-Power modes
of operation. When this pin goes high, the part is placed
into a Low-Power mode and the output is high-Z. When
this pin goes low, a calibration sequence is started
(which corrects VOS). At the end of the calibration
sequence, the output becomes low-impedance and the
part resumes normal operation.
An internal POR triggers a calibration event when the
part is powered on, or when the supply voltage drops
too low. Thus, the MCP622 parts are calibrated, even
though they do not have a CAL/CS pin.
3.6
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (
θJA).
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