參數(shù)資料
型號： MCP631T-E/OT
廠商： Microchip Technology
文件頁數(shù)： 16/62頁
文件大?。?/td> 0K
描述： IC OP AMP SGL 24MHZ SOT23-5
標(biāo)準(zhǔn)包裝： 3,000
放大器類型： 通用
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 10 V/µs
增益帶寬積： 24MHz
電流 - 輸入偏壓： 4pA
電壓 - 輸入偏移： 1800µV
電流 - 電源： 2.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 2.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SC-74A，SOT-753
供應(yīng)商設(shè)備封裝： SOT-23-5
包裝： 帶卷 (TR)
2009-2011 Microchip Technology Inc.
DS22197B-page 23
MCP631/2/3/4/5/9
The power de-rating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
EQUATION 4-5:
Several techniques are available to reduce
TJA for a
given POAmax:
Lower
JA
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
Reduce POAmax
- Increase RL
- Limit IOUT (using RSER)
- Decrease VDD
4.3
Improving Stability
4.3.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-6) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-6:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN =+2V/V).
FIGURE 4-7:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP631/2/3/4/5/9 SPICE macro
model are helpful.
4.3.2
GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
FIGURE 4-8:
Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/
V), which causes an increase in gain at high frequen-
cies. CG also reduces the phase margin of the feed-
back loop, which becomes less stable. This effect can
be reduced by either reducing CG or RF.
n
JA
TJmax –TA
POAmax
Where:
TJmax = absolute maximum junction temperature
RISO
VOUT
CL
RG
RF
RN
MCP63X
10
100
1,000
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Capacitance; CL/GN (F)
Reco
mm
en
ded
R
IS
O
(
)
GN = +1
GN +2
10p
100p
1n
10n
VP
RF
VOUT
RN
CN
VM
RG
CG
MCP63X
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MCP632T-E/MF 功能描述:運算放大器 - 運放 Dual 24MHz OP E temp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel
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