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| 型號： | MCP6546RT-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP 1.6V SNGL O-D SOT23-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，開漏極，軌至軌，TTL |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 7mV @ 5.5V |
| 電流 - 輸入偏壓（最小值）： | 1pA @ 5.5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 8µs |
| 磁滯： | 6.5mV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | SC-74A，SOT-753 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 681 (CN2011-ZH PDF) |
| 其它名稱： | MCP6546RT-E/OTDKR |
DS693F1
15
CS3318
5.2.2
Analog Outputs
The analog outputs are capable of driving 2k
short-circuit protected to 20 mA.
The minimum output load resistance is 2k
As the load resistance decreases, the potential for increased internal heating and the possibility of dam-
age to the device is introduced. Additionally, the load capacitance should be less than 100 pF. Increased
load capacitance may cause increased distortion, and the potential for instability in the output amplifiers.
If a low-impedance or high-capacitance load must be driven, an external amplifier should be used to iso-
late the outputs of the CS3318.
5.2.3
Recommended Layout, Grounding, and Power Supply Decoupling
As with any high-performance device that contains both analog and digital circuitry, careful attention must
be provided to power supply and grounding arrangements to optimize performance. Figure 3 on page 12
shows the recommended power arrangements, with VA+, VA-, and VD connected to clean supplies.
Power supply decoupling capacitors should be placed as near to the CS3318 as possible, with the low
value ceramic capacitor being the nearest. Care should be taken to ensure that there is minimal resis-
tance in the analog ground leads to the device to prevent any changes in the defined gain/attenuation set-
tings. The use of a unified ground plane is recommended for optimal performance and minimal radiated
noise. The CS3318 evaluation board demonstrates the optimum layout and power supply arrangements.
Should the printed circuit board have separate analog and digital regions with independent ground planes,
the CS3318 should reside in the analog region of the board.
Extensive use of ground plane fill on the circuit board will yield large reductions in radiated noise effects.
5.3
Power-Up and Power-Down
The CS3318 will remain in a completely powered-down state with the control port inaccessible until the RE-
SET pin is brought high. Once RESET is high, the control port will be accessible, but the internal amplifiers
will remain powered-down until the PDN_ALL bit is cleared.
To bring a channel out of power-down, both the PDN_ALL and the channel’s PDNx bit must be cleared. By
default, all channels’ PDNx bits are cleared, and the PDN_ALL bit is set. To minimize audible artifacts during
power-up process, the CS3318 automatically holds each channel’s volume at mute until its amplifier has
completed its power-up sequence. Once the power-up process is complete, each channel’s volume will au-
tomatically be set to the correct level according to the CS3318’s control port settings.
To place a channel in power-down, either the channel’s PDNx bit or the PDN_ALL bit must be set. To min-
imize audible artifacts during the power-down process, the CS3318 automatically places each channel in
mute before the amplifier begins its power-down sequence.
The power-up and power-down muting/volume changes are implemented as dictated by the zero-crossing
detection settings (see “Zero-Crossing Detection” on page 22). If an immediate power-up or power-down is
required, the zero-crossing mode should be set to immediate before changing the power-down state of the
device or channel.
Referenced Control
Register Location
PDN_ALL ............................ “Power Down All (Bit 0)” on page 35
PDNx ................................... “Channel Power - Address 0Dh” on page 35
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