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| 型號： | MCP669T-E/ML |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP QUAD 60MHZ 16QFN |
| 標準包裝： | 3,300 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 32 V/µs |
| 增益帶寬積： | 60MHz |
| 電流 - 輸入偏壓： | 6pA |
| 電壓 - 輸入偏移： | 1800µV |
| 電流 - 電源： | 6mA |
| 電流 - 輸出 / 通道： | 80mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
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2009-2012 Microchip Technology Inc.
DS22194D-page 23
MCP660/1/2/3/4/5/9
The power derating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
EQUATION 4-5:
Several techniques are available to reduce
TJA for a
given POAmax:
Lower
JA
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
Reduce POAmax
- Increase RL
- Limit IOUT (using RSER)
- Decrease VDD
4.3
Distortion
Differential gain (DG) and differential phase (DP) refer
to the non-linear distortion produced by an NTSC or a
phase-alternating line (PAL) video component. Table 1-
2 and Figure 2-34 show the typical performance of the
MCP661, configured as a gain of +2 amplifier (see
Figure 4-10), when driving one back-matched video
load (150
, for 75 cable). Microchip tests use a sine
wave at NTSC’s color sub-carrier frequency of 3.58
MHz, with a 0.286VP-P magnitude. The DC input volt-
age is changed over a +0.7V range (positive video) or
a -0.7V range (negative video).
DG is the peak-to-peak change in the AC gain magni-
tude (color hue), as the DC level (luminance) is
changed, in percentile units (%). DP is the peak-to-
peak change in the AC gain phase (color saturation),
as the DC level (luminance) is changed, in degree (°)
units.
4.4
Improving Stability
4.4.1
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the phase margin (stability) of
the feedback loop decreases and the closed-loop
bandwidth is reduced. This produces gain peaking in
the frequency response, with overshoot and ringing in
the step response. A unity gain buffer (G = +1) is the
most sensitive to capacitive loads, though all gains
show the same general behavior.
When driving large capacitive loads with these op
amps (e.g., >20 pF when G = +1), a small series resis-
phase margin of the feedback loop by making the out-
put load resistive at higher frequencies. The bandwidth
generally will be lower than bandwidth without the
capacitive load.
FIGURE 4-6:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-7:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for the circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify the value of RISO until the
response is reasonable. Bench evaluation and simula-
tions with the MCP660/1/2/3/4/5/9 SPICE macro model
are helpful.
n
JA
TJmax – TA
POAmax
Where:
TJmax = absolute max. junction temperature
RISO
VOUT
CL
RG
RF
RN
MCP66X
1
10
100
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Capacitance; CL/GN (F)
Re
c
o
m
en
d
ed
R
IS
O
(
)
GN = +1
GN +2
10p
100p
1n
10n
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