The bandwidth of these amplifiers depends on G
參數(shù)資料
型號(hào)： MCP6N11-005E/SN
廠商： Microchip Technology
文件頁數(shù)： 22/50頁
文件大小： 0K
描述： IC AMP INSTR RRIO 8SOIC
標(biāo)準(zhǔn)包裝： 100
放大器類型： 儀表
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 9 V/µs
增益帶寬積： 2.5MHz
電流 - 輸入偏壓： 10pA
電壓 - 輸入偏移： 850µV
電流 - 電源： 800µA
電流 - 輸出 / 通道： 30mA
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 管件
2011 Microchip Technology Inc.
DS25073A-page 29
MCP6N11
4.1.4
AC PERFORMANCE
The bandwidth of these amplifiers depends on GDM
and GMIN:
EQUATION 4-10:
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
for these parts:
EQUATION 4-11:
CMRR is constant from DC to about 1 kHz.
4.1.5
NOISE PERFORMANCE
As shown in Figures 2-41 and 2-42, the 1/f noise
causes an apparent wander in the DC output voltage.
Changing the measurement time or bandwidth has little
effect on this noise.
We recommend re-calibrating VOS periodically, to
reduce 1/f noise wander. For example, VOS could be
re-calibrated at least once every 15 minutes; more
often when temperature or VDD change significantly.
4.2
Functional Blocks
4.2.1
RAIL-TO-RAIL INPUTS
Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
crossover distortion vs. common mode voltage.
With this topology, the inputs (VIP and VIM) operate
normally down to VSS – 0.2V and up to VDD + 0.15V at
room temperature (see Figure 2-11). The input offset
voltage (VOS) is measured at VCM =VSS –0.2V and
VDD + 0.15V (at +25°C), to ensure proper operation.
4.2.1.1
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figures 2-18 and 2-50 show an input voltage
exceeding both supplies with no phase inversion.
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
see Figures 2-22 and 2-51.
4.2.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
Ratings ”). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
FIGURE 4-4:
Simplified Analog Input ESD
Structures.
Where:
fBW = -3 dB bandwidth
fGBWP = Gain bandwidth product
f
BW
f
GBWP
G
DM
---------------
≈
0.50 MHz
() G
MIN GDM
(),
≈
0.35 MHz
() G
MIN GDM
(),
≈
GMIN =1, …, 10
GMIN =100
Where:
V
O = Maximum output voltage swing
≈ VOH –VOL
f
FP BW
SR
πV
O
----------
≈
f
BW
≈
, for these parts
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIP
VSS
Input
Stage
Bond
Pad
VIM
of
INA Input
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