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| 型號： | MCP6V26-E/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP AUTO-ZERO SGL 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 自動(dòng)調(diào)零 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 1 V/µs |
| 增益帶寬積： | 2MHz |
| 電流 - 輸入偏壓： | 7pA |
| 電壓 - 輸入偏移： | 2µV |
| 電流 - 電源： | 620µA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
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2011 Microchip Technology Inc.
DS25007B-page 25
MCP6V26/7/8
4.3.6
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-7:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN2). The y-axis is
the normalized resistance (GNRISO).
GN is the circuit’s noise gain. For non-inverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-8:
Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6V26/7/8 SPICE macro
model are helpful.
4.3.7
STABILIZING OUTPUT LOADS
This family of auto-zeroed op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
resistance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(RL +RISO)||(RF +RG), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least (2 k
Ω)/GN.
FIGURE 4-9:
Output Load.
4.3.8
GAIN PEAKING
Figure 4-10 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG rep-
resent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and
non-inverting input pins.
FIGURE 4-10:
Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
RISO
CL
VOUT
U1
MCP6V2X
1
10
100
1000
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
CL/GN
2 (F)
Recommended
G
N
R
ISO
()
100p
1n
10n
100n
1μ
1
10
100
1k
GN = 1
GN = 2
GN = 5
GN 10
RG
RF
VOUT
RL
CL
U1
MCP6V2X
RF
CG
RN
VOUT
U1
MCP6V2X
RG
VM
VP
CFP
CN
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