參數(shù)資料
型號(hào): MCP79411-I/MS
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: ROHS COMPLAINT, PLASTIC, MSOP-8
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 584K
代理商: MCP79411-I/MS
MCP7941X
DS22266C-page 8
2010-2011 Microchip Technology Inc.
FIGURE 3-2:
ACKNOWLEDGE TIMING
3.1.2
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte consists of a control code; for the
MCP7941X this is set as ‘1010111X’ for read (0xAF)
and write (0xAE) operations for the EEPROM.
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’ (0xDF for a read, 0xDE
for a write). The RTCC registers and the SRAM share
the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
the data byte (Figure 3-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7941X monitors
the SDA bus, checking the device type identifier being
transmitted.
Upon
receiving
an
‘1010111’
or
‘1101111’
code,
the
slave
device
outputs
an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the MCP7941X will select a read
or write operation.
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
SCL
9
8
7
6
5
4
3
2
11
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
1
010
R/W
A7
A
0
EEPROM CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
{“A7” is ‘0’ for normal EEPROM
111
1
101
R/W
A7
A
0
SRAM RTCC CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111
operations, but is used to access unique ID
location and STATUS register.)
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