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參數(shù)資料
| 型號(hào)： | MCP79520T-I/MS |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTCC SPI 64B SRAM 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，EEPROM，閏年，方波輸出，SRAM，唯一 ID |
| 存儲(chǔ)容量： | 64B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 電壓 - 電源，電池： | 1.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
SY87739L
June 2011
11
M9999-061511
hbwhelp@micrel.com
This circuit further modifies the frequency generated by
the fractional-N loop. This comes in handy where digital
frequency and/or FEC is implemented. The wrapper
synthesizer generates just a few ratios near 1.
The wrapper modifies the frequency based on the values
of M and N, the dividers, as per:
540MHz
≤ f
WROUT =
+
×
=
×
P
1
P
1
P
FNOUT
Q
P
M
N
f
M
N
× f
REF ≤ 729MHz
Wrapper Phase-Frequency Detector
This circuit generates pump up and pump down signals
for the charge pump, and also generates delta phase for
the lock detector.
Wrapper Charge Pump
This circuit converts the pump signals from the phase-
frequency detector into current pulses. Charge pump
current is fixed at about 20A. An external loop filter
integrates these current pulses into a control voltage.
Wrapper VCO
This circuit matches the fractional-N VCO in construction
and operation, so that the center frequency trim circuit
can center both the fractional-N VCO and the wrapper
VCO at about the same frequency.
or (408) 955-1690
Wrapper M Divider
This circuit forms the denominator of the ratio by which
the wrapper synthesizer modifies the fractional-N output
frequency. The division ratio is selected via MicroWire,
as the 3-bit MdivSel register, as per Table 3.
MdivSel2
MdivSel1
MdivSel0
Divisor
0
16
0
1
16
0
1
0
18
0
1
17
1
0
31
1
0
1
14
1
0
32
1
15
Table 3. MdivSel Divisor Control
The divisors are in two sets. The first set consists of the
divisors 14, 15, 16, 17, and 18. The second set consists
of 31 and 32. Both M and N must be chosen from the
same set. For example, an N divisor of 31 and an M
divisor of 17 results in undefined behavior. The
M
N
ratio must be kept smaller than
14
17
, that is
14
18
is
not allowed.
Wrapper N Divider
This circuit forms the numerator of the ratio by which the
wrapper synthesizer modifies the fractional-N output
frequency. The division ratio is selected via MicroWire,
wrapper and/or FEC is implemented. The wrapper as the
3-bit NdivSel register, as per Table 4.
NdivSel2
NdivSel1
NdivSel0
Divisor
0
16
0
1
16
0
1
0
18
0
1
17
1
0
31
1
0
1
14
1
0
32
1
15
Table 4. NdivSel Divisor Control
The output of the wrapper synthesizer is post divided
down before appearing at the CLKOUT± pins. Notice
that, given the range of the wrapper VCO (540MHz to
729MHz) and the maximum and minimum division ratios
of the P divider (1 to 60, as shown in Table 5), the
minimum and maximum frequency of CLKOUT± is
10MHz and 729MHz respectively.
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