Chapter 5 Port Integration Module (PIM9KT256V1)
MC9S12KT256 Data Sheet, Rev. 1.16
190
Freescale Semiconductor
5.3.1.3
Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime.
This register congures each port T pin as either input or output. The TIM forces the I/O state to be an
output for each timer port associated with an enabled output compare. In these cases the data direction bits
will not change. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. The timer input capture always monitors the state of the pin.
5.3.1.4
Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime.
This register congures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
Module Base + 0x0002
76543210
R
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
Reset
0
00000
Figure 5-4. Port T Data Direction Register (DDRT)
Table 5-3. DDRT Field Descriptions
Field
Description
7–0
DDRT[7:0]
Data Direction Port T
0 Associated pin is congured as input.
1 Associated pin is congured as output.
Module Base + 0x0003
76543210
R
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
W
Reset
0
00000
Figure 5-5. Port T Reduced Drive Register (RDRT)
Table 5-4. RDRT Field Descriptions
Field
Description
7–0
RDRT[7:0]
Reduced Drive Port T
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.