參數(shù)資料
型號(hào)： MCV14A-I/SL
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
封裝： 3.90 MM, PLASTIC, SOIC-14
文件頁數(shù)： 20/82頁
文件大?。?/td> 1053K
代理商： MCV14A-I/SL
2009 Microchip Technology Inc.
Preliminary
DS41338C-page 27
MCV14A
5.4
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except RB3 which is input only,
may be used for both input and output operations. For
input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except RB3) can be programmed individually as
input or output.
FIGURE 5-1:
MCV14A EQUIVALENT
CIRCUIT FOR A SINGLE
I/O PIN
TABLE 5-2:
SUMMARY OF PORT REGISTERS
TABLE 5-3:
I/O PINS ORDER OF PRECEDENCE
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS
‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin
W
Reg
Latch
Reset
VSS
VDD
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A
TRIS
—
I/O Control Register (PORTB, PORTC)
--11 1111
N/A
OPTION
RBWU
RBPU
TOCS
TOSE
PSA
PS2
PS1
PS0
1111 1111
03h
STATUS
RBWUF CWUF
PA0
TO
PD
Z
DC
C
0001 1xxx
q00q quuu(1)
06h
PORTB
—
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
07h
PORTC
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
Legend: Shaded cells are not used by PORT registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown,
u
= unchanged,
q
= depends on condition.
Note 1:
If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
Priority
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC4
RC5
1
AN0
AN1
AN2
RB3/MCLR
C2IN+
C2IN-
CVREF
C2OUT
T0CKI
2
C1IN+
C1IN-
C1OUT
—
TRISC
3
TRISB
—
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