參數(shù)資料
型號(hào)： MCV18E-I/P
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP18
封裝： 0.300 INCH, LEAD FREE, PLASTIC, DIP-18
文件頁(yè)數(shù)： 23/108頁(yè)
文件大?。?/td> 1509K
代理商： MCV18E-I/P
2009 Microchip Technology Inc.
DS41399A-page 21
MCV18E
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
3.1
PORTA and the TRISA Register
PORTA is a 5-bit wide bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the PORT latch.
All write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the
PORT data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
PORTA pins, RA<3:0>, are multiplexed with analog
inputs and analog VREF input. The operation of each
pin is selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1:
INITIALIZING PORTA
FIGURE 3-1:
BLOCK DIAGRAM OF
RA<3:0>
Note:
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
Note:
Setting RA3:0 to output while in Analog
mode will force pins to output contents of
data latch.
BCF
STATUS, RP0
;
CLRF
PORTA
;Initialize PORTA by
;clearing output
;data latches
BSF
STATUS, RP0
;Select Bank 1
MOVLW
0xEF
;Value used to
;initialize data
;direction
MOVWF
TRISA
;Set RA<3:0> as inputs
;RA<4> as outputs
BCF
STATUS, RP0
;Return to Bank 0
DATA
BUS
Q
D
Q
CK
Q
D
Q
QD
EN
P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin
Analog
Input
mode
TTL
Input
Buffer
To A/D Converter
VSS
VDD
CK
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