OPERATIONAL MODES RST PIN DESCRIPTION A 337" />
參數(shù)資料
型號(hào)： MCZ33742EGR2
廠商： Freescale Semiconductor
文件頁數(shù)： 24/71頁
文件大?。?/td> 0K
描述： IC SYSTEM BASIS CHIP CAN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
電流 - 電源： 42mA
電源電壓： 5.5 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RST PIN DESCRIPTION
A 33742 output is available to perform a reset of the MCU. Reset can happen from:
VDD Falling Out of Range—If VDD falls below the reset threshold (VRSTTH), the RST pin is pulled LOW until VDD returns to
the normal voltage.
Power-ON Reset—At 33742 power-on or wake-up from Sleep mode, the RST pin is maintained LOW until VDD is within its
operation range.
Watchdog Timeout—If watchdog is not cleared, the 33742 will pull the RST pin LOW for the duration of the reset time
(tRSTDUR).
RST AND WDOG OPERATION
Table 8 describes watchdog and reset output modes of operation. RST is activated in the event VDD fall or watchdog is not
triggered. WDOG output is active LOW as soon as RST goes LOW and stays LOW as long as the watchdog is not properly reset
via SPI. The WDOG output pin is designed as a push-pull structure that can drive off chip components signaling, for instance,
errant MCU operation.
Figure 12 illustrates the device behavior in the event the TIM1 register in not properly accessed. In this case, a software reset
occurs and the WDOG pin is set LOW until the TIM1 register is properly accessed.
Table 8. Watchdog and Reset Output Operation
Events
WDOG
Output
RST Output
Device Power up
LOW to HIGH
VDD Normal, WDOG Properly Triggered
HIGH
VDD < VRSTTH
HIGH
LOW
WDOG Timeout Reached
LOW (42)
LOW
Notes
42.
WDOG stays LOW until the TIM1 register is properly addressed through SPI.
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