參數(shù)資料
型號: MCZ33790EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Two-Channel Distributed System Interface (DSI) Physical Interface Device
中文描述: 雙通道分布式系統(tǒng)接口(DSI)的物理接口設(shè)備
文件頁數(shù): 6/12頁
文件大?。?/td> 180K
代理商: MCZ33790EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
33790
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
V
DD
5.25 V, 8.0 V
V
SUP
25.0 V, -40
°
C
T
J
150
°
C unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
MICROCONTROLLER INTERFACE
Microcontroller Signal Cycle Time
t
CYC
6.6
1000
μ
s
Microcontroller Signal Low Time
t
CYCL
2.0
667
μ
s
Microcontroller Signal High Time
t
CYCH
2.0
667
μ
s
Microcontroller Signal Duty Cycle for Logic Zero
DC
LO
30
33
36
%
Microcontroller Signal Duty Cycle for Logic One
DC
HI
60.0
66.7
72.0
%
Microcontroller Signal Slew Time
(6)
t
SLEW
500
ns
Frame Start to Signal Delay Time
t
DLY1
t
cyc
- 0.1
t
cyc
t
cyc
+ 0.1
μ
s
Signal End to Frame End Delay Time
t
DLY2
1.0
μ
s
Rise Time
(6)
t
RISE
0
100
ns
Fall Time
(6)
t
FALL
0
100
ns
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate
C
5.0 nF
t
SLEW
(FRAME)
3.0
6.0
10.0
V/
μ
s
Signal High to Low and Signal Low to High Slew Rate
C
5.0 nF
t
SLEW
(SIGNAL)
3.0
4.5
8.0
V/
μ
s
Data Valid (V
SUP
x
= 25 V, C
L
5.0 nF)
DSIxF, V
IN(TH)
to DSIxO = 5.3 V
DSIxS, V
IN(TH)
to DSIxO = 2.6 V
DSIxS, V
IN(TH)
to DSIxO = 3.4 V
DSIxF, V
IN(TH)
to DSIxO = 7.0 V
t
DVLD1
t
DVLD2
DVLD3
DVLD4
2.44
0.25
0.25
0.25
6.56
1.3
1.3
1.3
μ
s
BUS RECEIVER
Receiver Delay Time
t
DRH
: I = I
RH
to DSIxR = 2.5 V
t
DRL
: I = I
RH
to DSIxR = 2.5 V
t
DRH
t
DRL
400
400
750
750
ns
Notes
6.
Slew times and rise and fall times between 10% and 90% of output high and low levels.
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