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參數(shù)資料
| 型號： | MCZ33903B5EKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 37/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SBC CAN HS 5.0V 32SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 系統(tǒng)基礎(chǔ)芯片 |
| 接口： | CAN，LIN |
| 電源電壓： | 5.5 V ~ 28 V |
| 封裝/外殼： | 32-BSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-SOICW 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
36
Freescale Semiconductor
33903/4/5
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VAUX is controlled via the SPI, and can be turned ON or
OFF. VAUX low threshold detection and overcurrent
information will disable VAUX, and are reported in the SPI and
can generate INT.
VAUX is OFF by default and must be turned ON by the SPI.
UNDERVOLTAGE RESET AND RESET FUNCTION
(RST)
The RST pin is an open drain structure with an internal
pull-up resistor. The LS driver has limited current capability
when asserted low, in order to tolerate a short to 5.0 V. The
RST pin voltage is monitored in order to detect failure (e.g.
RST pin shorted to 5.0 V or GND).
The RST pin reports an undervoltage condition to the MCU
at the VDD pin, as a RST failure in the watchdog refresh
operation. VDD undervoltage reset also operates in LP VDD
ON mode.
Two VDD undervoltage thresholds are included. The upper
(typically 4.65 V, RST-TH1-5) can lead to a Reset or an
Interrupt. This is selected by the SPI. When “RST-TH2-5“is
selected, in Normal mode, an INT is asserted when VDD falls
below “RST-TH1-5“, then, when VDD falls below “RST-TH2-5” a
Reset will occur. This will allow the MCU to operate in a
degraded mode (i.e., with 4.0 V VDD).
I/O PINS (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used
for small loads or to drive external transistors. When used as
output drivers, the I/Os are either a HS or LS type. They can
also be set to high-impedance. I/Os are controlled by the SPI
and at power on, the I/Os are set as inputs. They include
overload protection by temperature or excess of a voltage
drop.
When I/O-0/-1/-2/-3 voltage is greater than VSUP/2
voltage, the leakage current (II/O_LEAK) parameter is not
applicable
I/O-0 and I/O-1 will have current flowing into the device
through three diodes limited by an 80 kOhm resistor (in
series).
I/O-2 and I/O-3 will have unlimited current flowing into the
device through one diode.
In LP mode, the state of the I/O can be turned ON or OFF,
with extremely low power consumption (except when there is
a load). Protection is disabled in LP mode.
When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-
1, -2 and -3 are the wake inputs.
I/O-2 and I/O-3 pins share the LIN Master pin function.
VSENSE INPUT (VSENSE)
This pin can be connected to the battery line (before the
reverse battery protection diode), via a serial resistor and a
capacitor to GND. It incorporates a threshold detector to
sense the battery voltage and provide a battery early
warning. It also includes a resistor divider to measure the
VSENSE voltage via the MUX-OUT pin.
MUX-OUTPUT (MUXOUT)
The MUX-OUT pin (Figure 22) delivers an analog voltage
to the MCU A/D input. The voltage to be delivered to MUX-
OUT is selected via the SPI, from one of the following
functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V
reference, die temperature sensor, VDD current copy.
Voltage divider or amplifier is inserted in the chain, as
shown in Figure 22.
For the VDD current copy, a resistor must be added to the
MUX-OUT pin, to convert current into voltage. Device
includes an internal 2.0 k resistor selectable by the SPI.
Voltage range at MUX-OUT is from GND to VDD. It is
automatically limited to VDD (max 3.3 V for 3.3 V part
numbers).
The MUX-OUT buffer is supplied from 5 V-CAN regulator,
so the 5 V-CAN regulator must be ON in order to have:
1) MUX-OUT functionality and
2) SPI selection of the analog function.
If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND
and the SPI command that selects one of the analog inputs
is ignored.
Delay must be respected between SPI commands for 5 V-
CAN turned ON and SPI to select MUX-OUT function. The
delay depends mainly upon the 5 V-CAN capacitor and load
on 5 V-CAN.
The delay can be estimated using the following formula:
delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN.
C = cap at 5 V-CAN regulator, U = 5.0 V,
I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator
(parameter 5 V-C ILIM).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCZ33903B5R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
| MCZ33903BD3EK | 功能描述:CAN 接口集成電路 Canvas 32 DL (3.3V) RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33903BD3EKR2 | 功能描述:CAN 接口集成電路 Canvas 32 DL (3.3V) RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33903BD3R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
| MCZ33903BD5EK | 功能描述:CAN 接口集成電路 SBC W/HIGH SPEED CAN 5V RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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